第二章 系统架构浏览2.5
2.5 CONTROL REGISTERS控制寄存器
Control registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-6) determine operating
mode of the processor and the characteristics of the currently executing task.
These registers are 32 bits in all 32-bit modes and compatibility mode.
In 64-bit mode, control registers are expanded to 64 bits. The MOV CRn instructions
are used to manipulate the register bits. Operand-size prefixes for these instructions
are ignored. The following is also true:
控制寄存器（CR0,CR1,CR2,CR3,CR4,看图2-6）决定处理器的运行模式，以及当前执行程序的一些特性。在所有32位模式以及其兼容模式下，这些寄存器都是32位的。
在64位模式下，控制寄存器扩展至64位。指令MOV CRn用于操作寄存器的位。该操作指令的前缀操作数的大小被忽略。
下面描述的内容位真：
• Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros. Writinga nonzero value to any of the upper 32 bits results in a general-protectionexception, #GP(0).
CR0,CR4寄存器的位32至位63保留，必须设为0.向这些为设值会诱发一个保护中断#GP(0).
• All 64 bits of CR2 are writable by software.
CR2的64个位对于软件都是可写的。
• Bits 51:40 of CR3 are reserved and must be 0
CR3的位40至位52保留，必须清零。
• The MOV CRn instructions do not check that addresses written to CR2 and CR3are within the linear-address or physical-address limitations of the implementation.
指令MOV CRn不对将要写入CR2和CR3的地址做合法性的检查，即检查是否在合法的线性地址空间或者合法的物理地址空间。
• Register CR8 is available in 64-bit mode only.
CR8只有在64模式才可用
The control registers are summarized below, and each architecturally defined controlfield in these control registers are described individually. In Figure 2-6, the width of
the register in 64-bit mode is indicated in parenthesis (except for CR0).
控制寄存器如下综述。每个架构都在控制寄存器里定义了控制块。稍后会对这些控制寄存器进行独立的描述。图26表明这些寄存器的大小是64位（除了CR0）.
• CR0 — Contains system control flags that control operating mode and states of the processor.
包含系统控制标识，用以控制处理器的运行模式和状态
• CR1 — Reserved.保留
• CR2 — Contains the page-fault linear address (the linear address that caused apage fault).
包含页面错误的线性地址（诱发页面错误的线性地址）
• CR3 — Contains the physical address of the base of the page directory and two flags (PCD and PWT). This register is also known as the page-directory base register (PDBR). Only the most-significant bits (less the lower 12 bits) of the base
address are specified; the lower 12 bits of the address are assumed to be 0. The page directory must thus be aligned to a page (4-KByte) boundary. The PCD and PWT flags control caching of the page directory in the processor’s internal data
caches (they do not control TLB caching of page-directory information).
CR3包含页目录的物理基地址和两个标识（PCD 和PWT）.这个处理器也通常作为页目录基地址寄存器(PDBR).只有基地址中最重要的位（低12位）才会被指明；地址的低12位通常假设其值为0.页表必须与页的分界线（4KB）对齐。PCD 和PWT标识控制处理器内部数据缓冲中的页表缓冲（这两个标识不控制页表信息中的TLB缓冲）
When using the physical address extension, the CR3 register contains the base address of the page-directory-pointer table In IA-32e mode, the CR3 register contains the base address of the PML4 table.
当使用物理地址的扩展特性时，CR3寄存器包含的是页目录指针表的基地址。在IA32E模式下，CR3寄存器包含了PML4表的基地址。
• CR4 — Contains a group of flags that enable several architectural extensions,and indicate operating system or executive support for specific processor capabilities.
The control registers can be read and loaded (or modified) using the moveto-or-from-control-registers forms of the MOV instruction. In protected mode,the MOV instructions allow the control registers to be read or loaded (at privilege level 0 only). This restriction means that application programs or operatingsystem procedures (running at privilege levels 1, 2, or 3) are prevented from reading or loading the control registers.
CR4寄存器包含一组标识，这些标识用于激活架构的一些扩展特性，并且标明操作系统或服务程序为处理器的一些特殊的特性做的一些支持。
通过MOV指令，CR4寄存器可以被导入或读取或修改。在保护模式下，MOV指令可以对CR4寄存器进行导入或读取的操作（只有在等级0的情况下才允许）。这条约束意味着，操作系统或执行程序在登记1，2，3的情况下都不被允许对CR4寄存器惊醒导入或读取的操作。
• CR8 — Provides read and write access to the Task Priority Register (TPR). It specifies the priority threshold value that operating systems use to control the priority class of external interrupts allowed to interrupt the processor. This register is available only in 64-bit mode. However, interrupt filtering continues to apply in compatibility mode.
CR8寄存器提供关于读和写任务优先权寄存器的权限信息。被允许产生中断电外部中断都有优先权等级；优先权的等级是有操作系统去控制；而CR8提供了处理器用以控制优先权的优先权临界值。CR8寄存器只在64位模式才可用。但是，兼容模式仍然提供了中断屏蔽的功能。
When loading a control register, reserved bits should always be set to the values previously read. The flags in control registers are:
导入控制寄存器的值是，保留的位必须一直保留上一次读到的值。控制寄存器里的标识如下：
PG Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) is not also set; setting the PG flag when the PE flag is clear causes a general protection exception (#GP)。On Intel 64 processors, enabling and disabling IA-32e mode operation also requires modifying CR0.PG.
PG 分页（CR0的位31） 该标识设值时，激活分页功能；清零则禁用分页功能。禁用分页时，所有的线性地址都被当作物理地址看待。如果PE标识（CR0的位0）未设值，则PG标识无任何作用。在PE标识清零的情况下，对PG标识进行设值会引发一个保护中断（#GP）。对于intel64位处理器来说，激活和禁用IA32E模式的操作同样需要修改CR0寄存器的PG标识。
CD Cache Disable (bit 30 of CR0) — When the CD and NW flags are clear,caching of memory locations for the whole of physical memory in the processor’s internal (and external) caches is enabled. When the CD flag is set, caching is restricted as described in Table 10-5. To prevent the processor
from accessing and updating its caches, the CD flag must be set and the caches must be invalidated so that no cache hits can occur.
CD 缓存禁用（CR0的位30）：当CD标识和NW标识同时清零时，内存缓存中的处理器内部和外部缓存被激活。当CD标识设值时，对缓存的约束有表10-5所综述。位防止处理器访问和更新它自己的缓存，CD标识必须设值，并且缓存必须置成无效，防止缓存请求的发生。
NW Not Write-through (bit 29 of CR0) — When the NW and CD flags are clear, write-back (for Pentium 4, Intel Xeon, P6 family, and Pentium processors) or write-through (for Intel486 processors) is enabled for writes that hit the cache and invalidation cycles are enabled. See Table 10-5 for detailed information about the affect of the NW flag on caching for other settings of the CD and NW flags.???
AM Alignment Mask (bit 18 of CR0) — Enables automatic alignment checking when set; disables alignment checking when clear. Alignment checking is performed only when the AM flag is set, the AC flag in the EFLAGS register is set, CPL is 3, and the processor is operating in either protected or virtual-
8086 mode.
AM 数据对齐屏蔽（CR0的位18）：当该标识设值时，激活数据的自动对齐；清零时则禁用数据对齐检查。只有在处理器在保护模式或者虚拟8086模式下运行，并且处理器权限（CPL）等级3，EFLAGS寄存器里的AC标识设值，以及AM标识设值，数据对齐检查才会执行。
WP Write Protect (bit 16 of CR0) — Inhibits supervisor-level procedures from writing into user-level read-only pages when set; allows supervisor-level procedures to write into user-level read-only pages when clear (regardless of the U/S bit setting; see Section 3.7.6). This flag facilitates implementation of the copy-on-write method of creating a new process (forking) used by operating
systems such as UNIX.
WP 写保护（CR0的位16）：当该位设值时，阻止超级用户的程序对一般用户级别的只读页面进行写操作；清零则允许。这个标识降低了操作系统创建新进程的copy-on-write方法的实现难度，比如UNIX的fork方法。
NE Numeric Error (bit 5 of CR0) — Enables the native (internal) mechanism for reporting x87 FPU errors when set; enables the PC-style x87 FPU error reporting mechanism when clear. When the NE flag is clear and the IGNNE#
input is asserted, x87 FPU errors are ignored. When the NE flag is clear andthe IGNNE# input is deasserted, an unmasked x87 FPU error causes the processor to assert the FERR# pin to generate an external interrupt and to stop instruction execution immediately before executing the next waiting
floating-point instruction or WAIT/FWAIT instruction.
The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR# pin are used with external logic to implement PC-style error reporting.
NE 数值错误（CR0的位5）：设值是激活举报X87 FPU错误的内部策略；清零时激活PC-Style X87 FPU错误的举报方法。
ET Extension Type (bit 4 of CR0) — Reserved in the Pentium 4, Intel Xeon, P6
family, and Pentium processors. In the Pentium 4, Intel Xeon, and P6 family
processors, this flag is hardcoded to 1. In the Intel386 and Intel486 processors,
this flag indicates support of Intel 387 DX math coprocessor instructions
when set.
TS Task Switched (bit 3 of CR0) — Allows the saving of the x87
FPU/MMX/SSE/SSE2/ SSE3 context on a task switch to be delayed until an
x87 FPU/MMX/SSE/SSE2/SSE3 instruction is actually executed by the new
task. The processor sets this flag on every task switch and tests it when
executing x87 FPU/MMX/SSE/SSE2/SSE3 instructions.