s3c6410硬件DISPLAY CONTROLLER（显示控制器）

1、OVERVIEW

LCD driver interface has four kinds of interface, i.e. the conventional RGB-interface, I80 Interface and  NTSC/PAL standard TV  Encoder Interface and IT-R BT. 601 interface. The DISPLAY controller supports up to 5 overlay image windows. Overlay image windows support various color format, 16 level alpha blending, color key, x-y position control, soft scrolling, variable window size, and etc.The DISPLAY controller supports various color formats such as RGB (1BPP to 24 BPP), and YCbCr 4:4:4(only local bus).

LCD 驱动接口有四种接口，如传统的RGB 接口，I80 接口，NTSC/PAL 标准TV 编码器接口和IT-R BT.601 接口。显示控制器支持5 层图像窗口。覆盖图像窗口支持多种颜色格式、16 级alpha 混合、color key，横纵坐标位置控制，软动，可变窗口尺寸等等。显示控制器支持各种颜色格式，如RGB（1BPPto24BPP），YcbCr4：4：4.

The DISPLAY controller is used to transfer the video data and to generate the necessary control signals such as,
RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, and SYS_CS0(as well as the control signals). DISPLAY
controller has the data ports for video data, which are RGB_VD[23:0], SYS_VD[17:0], and TV_OUT as shown in
Figure 14-1.

显示控制器用来转换视频数据，并产生需要的控制信号，如，RGB_VSYNC, RGB_HSYNC, RGB_VCLK,
RGB_VDEN 和SYS-CS0（作为控制信号）。显示控制器有视频数据端口，这些数据端口是RGB_VD[23:0]和
SYS_VD[17:0]，TV_OUT 如图14-1 所示。

2、FEATURES

Video Output Interface ：接口

RGB IF (Parallel)
RGB IF (Serial)
I80 Interface
TV Encoder Interface (NTSC, PAL standard)
ITU-R BT.601 interface (YUV422 8bit)

3、FUNCTIONAL DESCRIPTION

3.1、BRIEF OF THE SUB-BLOCK子模块简要

The DISPLAY controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator。

显示控制器由这些子模块组成。

The VSFR includes programmable register sets and two-256x 25 palette（调色板） memories.

The VDMA is a dedicated display DMA.

The VPRCS receives the video data from VDMA and sends the video data through the data ports to the display device (LCD) after converting them into a suitable data format, for example 8-bit per pixel mode (8 BPP Mode) or 16-bit per pixel mode (16 BPP Mode).

VPRCS 接收VDMA 发出的视频数据，将其转换到适合的数据格式，如8 位像素或16 位像素后，将视频数据发送到显示设备上。

The VTIME consists of programmable logic to support the variable requirement of interface timing and rates  commonly found in different LCD drivers.

3.2、DATA FLOW数据流

FIFO is present in the VDMA.The DISPLAY controller has five FIFOs because it needs to support the overlay window display mode.

显示控制器有5 个FIFO ，因为显示控制器需要支持覆盖窗口显示模式。

3.3、INTERFACE接口

DISPLAY controller supports 4 types of display device. One type is the conventional RGB-interface, which uses
RGB data, Vertical/horizontal sync, data valid signal and data sync clock. The Second type is I80 Interface which
uses address, data, chip select, read/write control and register/status indicating signal. In this type of LCD driver it
has a frame buffer and has the function of self-refresh, therefore DISPLAY controller updates one still image by
writing only one time to the LCD. The Third type is ITU-R BT.601 interface. ITU-R BT.601 interface uses YUV
data, Vertical/horizontal sync, optional Field signal, data valid signal and data sync clock. The fourth type is FIFO
interface with TV Encoder.

显示控制器支持4 个类型的显示设备。1 为传统的RGB 接口类型，使用RGB 数据，垂直/水平同步，数据有效信号数据同步时钟。第二种类型是I80 接口，使用地址，数据，芯片选择，以及读/写控制和寄存器/状态指示信号。在这种类型的LCD 设备内有一个帧缓冲区，可以进行自动刷新。因此，显示控制器一次只能向LCD 上传一个静态图像。第三种类型是ITU_R BT.601 接口，使用YUV 数据，垂直/水平同步，可选字段信号，数据有效信号和数据同步时钟。第四种类型是有TV 编码器的FIFO 接口。

3.4、OVERVIEW OF THE COLOR DATA颜色数据概要

举个例子：

NOTES:
1. AEN : Transparency value selection bit
AEN = 0 : ALPHA0_R/G/B values are applied
AEN = 1 : ALPHA1_R/G/B values are applied
If per-pixel blending is set, then this pixel would be blended with alpha value selected by AEN. Alpha value is selected by SFR value as ALPHA0_R, ALPHA0_G, ALPHA0_B, ALPHA1_R, ALPHA1_G, ALPHA1_B. For more information refer to description of SFR.
2. D[23:16] = Red data, D[15:8] = Green data, D[7:0] = Blue data

4、PALETTE USAGE调色板的使用

4.1、Palette Configuration and Format Control调色板配置和格式控制

The DISPLAY controller can support the 256 colors palette for various selection of color mapping.
The user can select 256 colors from the 25-bit colors through these four formats.
256 color palette consist of the 256(depth) × 25-bit DPSRAM. Palette supports 8:8:8, 6:6:6, 5:6:5(R:G:B), and etc
formats.

显示控制器支持256 种颜色的调色板，可以进行颜色映射的各种的选择。用户可以通过四种格式从25 位颜色中选择256 颜色。256 颜色调色包由256x25 位DPSRAM 组成。调色板支持8:8:8,6:6:6,5:6:5(R:G:B)等格式。

For example of A:5:5:5 format, write palette as specified in Table 14-2 and then connect VD pin to TFT LCD
panel( R(5)=VD[23:19], G(5)=VD[15:11], and B(5)=VD[7:3] ). The AEN bit controls the blending function enable or
disable. At the end, Set Window Palette Control (W0PAL, case window0) register to 0’b101.

例如A:5:5:5 格式，如表14-2 所示写调色板，将VD 管脚与TFT LCD 控制板相连
（R(5)=VD[23:19],G(5)=[15:11],B(5)=[7:3]）.AEN 位控制混合功能可以使能或禁止。最后，设置窗口调色板控制寄存器位0’b101.

4.2、WINDOW BLENDING窗口混合

The main function of the VPRCS module is window blending. DISPLAY controller has 5 window layers and the
details are described below.

VPRCS 模块的主要功能是窗口混合。显示控制器有5 个窗口层，具体层的内容接下来会有具体的描述。

4.3、COLOR-KEY FUNCTION

5、VTIME CONTROLLER OPERATION     VTIME 控制器操作

VTIME is mainly divided into two blocks. One is VTIME_RGB_TV for RGB interface, ITU-R601 interface and TV
Encoder Interface timing control. The other is for I80 interface timing control.

VTIME 主要分为两个模块。一个是VTIME_RGB_TV 模块，用于RGB 接口，ITU_R601 接口和TV编码器接口时序控制。另一个是用于I80 接口时序控制的模块。

5.1、RGB Interface

   The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK
signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2
registers in the VSFR register. 

   Based on these programmable configurations of the display control registers inVSFR, the VTIME module can generate the programmable control signals suitable for the support of manydifferent types of display device.

  The RGB_VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The
RGB_VSYNC and RGB_HSYNC pulse generation is controlled by the configuration of both the HOZVAL field and
the LINEVAL registers. 

The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to
the following equations:
HOZVAL = (Horizontal display size) -1
LINEVAL = (Vertical display size) –1
The rate of RGB_VCLK signal can be controlled by the CLKVAL field in the VIDCON0 register. The table below
defines the relationship of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.
RGB_VCLK (Hz) =HCLK/ (CLKVAL+1) where CLKVAL >= 1

VTIME 产生控制信号，如RGBZ-VSYNC,RGB_HSYNC,RGB_VDEN 和RGB_VCLK 信号。这些控制信号与VSFR 寄存器内的VIDTCON0/1/2 寄存器的配置有很大的关系。

根据VSFR 内显示控制寄存器的可编程配置，VTIME 模块可以产生程序控制信号，这些控制信号适合于很多不同类型的显示设备。
RGB_VSYNC 信号用来导致LCD 行指针从显示的顶层开始覆盖。RGB_VSYNC 和RGB_HSYNC 跳动产生由HOZVAL 区域和LINEVAL 寄存器的配置控制。HOZVAL 和LINEVAL 由LCD 显示屏的尺寸决定，具
体等式如下：
HOZVAL=(水平显示尺寸)-1
LINEVAL=(垂直显示尺寸)-1
RGB_VCLK 信号的速率可以由VIDCON0 寄存器内的CLKVAL 领域控制。RGB_VCLK 和CLKVAL之间的关系见表14-4. CLKVAL 最小值为1.
RGB_VCLK(Hz)=HCLK/(CLKVAL+1) CLKVAL>=1

The frame rate is calculated as follows;
Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } x { ( CLKVAL+1 ) / ( Frequency of Clock source ) } ]

5.2、LDI Command Control

LDI can receive command and data. Command refers to index for the selection of SFR in LDI. In control signal for
command and data, only SYS_RS signal has different operation. Generally, SYS_RS is polarity of ‘1’ for
command issue and vice versa.
DISPLAY Controller has two kinds of command control. One is auto command and the other is normal command.
Auto command is issued automatically (i.e. without S/W control) at a predefined rate (rate = 2,4, 6 ..30. Rate = 4
means auto command are send to LDI at the end of every 4-image-frames). Normal command is issued by S/W
control.

LDI 可以接收命令和数据。命令表示LDI 内的SFR 选择的索引。在命令和数据的控制信号内，只有SYS_RS 信号有不同的操作。通常SYS_RS 的命令极性是1，反之亦然。
显示控制器有两种命令控制形式。一种是自动命令控制形式，另一种是常规命令控制形式。自动命令
在预定速率内自动发出。通过S/W 控制可以发出常规命令。

5.3、RGB INTERFACE IO