FPGA debug notes
1. FPGA env, download and usage
1.1 Prepare power supply DC9.0V;
1.2 Prepare two USB cables, one for downloading bitfile, the other one for images;
1.3 Prepare and install usb driver, serial comm driver and trace32 tools;
1.4 Download bootrom via trace32;
1.5 Check ddr is right or wrong;
1.6 Find out BitFile and download to FPGA;
1.7 Choose the corresponding android version for FPGA, such as sprdroid4.4_3.10_sharkl_dev
1.8 Choose the corresponding compilation project, such as scx35_sp9630fpga-userdebug-native
1.9 Compile the source code, such as make bootloader or make bootimage
1.10 Download boot.img(kernel) and u-boot.bin(u-boot);
1.11 Use trace32 to run u-boot;
2. Light up panel of nt35516 in u-boot on FPGA platform
LIBS += drivers/video/sprdfb/libsprdfb.o ifdef CONFIG_DSIH_VERSION_1P21A LIBS += drivers/video/sprdfb/dsi_1_21a/libsprdfb_dsi.o else LIBS += drivers/video/sprdfb/dsi_1_10a/libsprdfb_dsi.o endif LIBS += drivers/video/sprdfb/lcd/liblcd.o LIBS += property/libproperty.odriver/video/sprdfb/dsi_1_21a:
include $(TOPDIR)/config.mk
LIB := $(obj)libsprdfb_dsi.o
#ifdef CONFIG_LCD
COBJS-$(CONFIG_DSIH_VERSION_1P21A) += mipi_dsih_api.o mipi_dsih_dphy.o mipi_dsih_hal.o
#endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
3 lvds work global setting
// enable
0x20e0_0000: bit[0] // DISPC en
0x402e_0004: bit[11] // Matrix en
// CLK cfg
0x7130_0000: bit[18] // CLK cfg en
// CLK_DISPC
0x2150_002c: bit[1:0] // CLK src (0-153.6M, 1-192M, 2-256M, 3-307.2M)
0x2150_002c: bit[10:8] // Dividor
// CLK_DBI
0x2150_0030: bit[1:0] // CLK src (0-128M, 1-153.6M, 2-192M, 3-256M)
0x2150_0030: bit[10:8] // Dividor
// CLK_DPI
0x2150_0034: bit[1:0] // CLK src (0-128M, 1-153.6M, 2-192M, 3-256M)
0x2150_0034: bit[10:8] // Dividor
0x2150_0034: bit[16] // CLK from LVDS TX (need set when in LVDS mode)
// RST
0x20e0_0004: bit[0] // DISPC reset
0x20e0_0004: bit[4] // Matrix reset
// LVDS cfg
0x402b_00a4: bit[0] // LVDS AP select
0x402e_3060: bit[0] // LVDS TX power down (active '1')
0x402e_0064: // LVDS PLL CFG1 (cfg later)
0x402e_0068: // LVDS PLL CFG2 (cfg later)
// IRQ
INTC1: bit[14]
/* Configure RGB mode, such as timing, data width, LCD reset, color, resolution, dpi and so on */ DISPC_ResetLCD_RGB_Mode(lcd_cfg); /* bit[16] clk from LVDS TX (need set when in LVDS mode) */ REG_SET(0x21500034, 16, 1); /* a4, bit[0]: LVDS AP select */ /* 60, bit[0]: LVDS TX power down (active '1') */ REG_SET(0x402b00a4, 0, 1); REG_SET(0x402e3060, 0, 1); /* '0': R/G/B[1:0] sent by lan3; '1': RGB[7:6] sent by lan3 */ TB_REG_OR(DISPC_LVDS_CTRL, BIT(21));
DISPC refresh background color:
4 trace32 using skill
4.1 data dump
Issue:
data.dump <address>
data.dump address++len
data.dump 0x20800000++100
data.dump address--address
data.dump 0x20800000--0x20801000
4.2 data.list and data.load
list source code and assemble.
The following two commands can be added to load excutable files and load source codes
D.LOAD \path\..axf
D.LOAD \path\...axf /nocode /STRIPPART 4 /SOURCEPATH \path\source codes
4.3 breakpoint
1). break.list // watch the list of breakpoint, meanwhile, the breakpoint can be disabled or enabled on this interface;
2). you just need to press "go", then the breaked code will be shown automatically, meanwhile, breakpoint can be added or deleted dynamically;
3). Show stack can show what is called currently;
4). "F4" -> Go Next; "F2" -> Come into every function; "F7" -> Go; "F8" -> Break;
5). If you wanna modify Break's implementation, click down: Break-> Implementation -> OnChip
4.4 show picture on trace32
# data.image 0x80080000 1024. 600. /RGB565LE This command can be used to show a picture.
4.5 save and load picture
D.LOAD PATH/pic.raw addr D.SAVE.BINARY PATH/pic.raw addr++offset e.g: 1024 * 600 * 2 == 0x12c000 D.SAVE.BINARY "D:\pic.raw" 0x80003718++0x12c000
4.6 example
Note: DDR2 or DDR1 should be initialized before loading axf file.
&BOOT=".\CA53_boot_64to32.axf" &DDR2_INIT="D:\...\ddr2_init.axf" system.mode down system.reset system.jtagclock 20mhz ; jtag clock should be set larger. system.cpu CORTEXA53 system.config CORENUMBER 1. core.assign 1 system.config corebase 0x80410000 system.config ctibase 0x80420000 system.config MEMORYACCESSPORT 0 system.config DEBUGACCESSPORT 1 system.mode Prepare system.mode Up WAIT 1.s D.LOAD "&BOOT" ; this axf should be after ddr1 or ddr2 is initialized. D.L G WAIT 2.s Break ; init DDR2 D.LOAD "&DDR2_INIT" G WAIT 6.s Break ; This position can initialize axf too Break.Delete D.LOAD D:\...\minicode.axf D.LOAD D:\...\minicode.axf /nocode /STRIPPART 4 /SOURCEPATH \PATH\minicode Break.Set test_entry WinCLEAR ; start x,y and width, height WinPOS 0. 0. 80. 40. data.dump 0x20800000 WinPOS 0. 40. 80. 40. data.dump 0x21800000 WinPOS 40. 0. 80. 40. V.WATCH dispc_regs go
5 mipi panel debug notes
1) dispc module enable;
2) dispc clock enable and set divider
3) dispc reset
4) dsi host reset
5) dispc internal enable // after DSI reset
6) set timing (HFP/HBP; VFP/VBP)
7) data width // 24bits / 18bits / 16bits
8) reset lcd
9) set dispc interface mode to DPI or eDPI
10) ...
6 dispc debug notes
6.1 refresh background color
0xFF0000: Red
0x00FF00: Green
0x0000FF: Blue
0xFFFFFF: White
0x000000: Black
0x20 -> 0x0; 0x40 -> 0x0; 0x3c -> 0xff0000; 0x80 BIT[5] -> 1
6.2 synopsys d-phy status (GENERAL 1, dsi host 1.21a)
6.2.1. When FPGA is powered up, the following leds are lighten up
TX_RXZ
DIRECTION_0
ENABLE_1
ENABLE_0
6.2.2. call mipi_dsih_dsih_open.
1). First, call mipi_dsih_dphy_open
mipi_dsih_dphy_reset(phy, 0); // place the digital section of D-PHY in the reset state;
mipi_dsih_dphy_stop_wait_time(phy, 0x1C); //stop wait time and initialize lane number to one lane;
mipi_dsih_dphy_no_of_lanes(phy, 1); // init to 1 lane first
mipi_dsih_dphy_clock_en(phy, 1); // Enable D-PHY Clock lane module,;
mipi_dsih_dphy_shutdown(phy, 1); // place D-PHY macro in power-on state;
mipi_dsih_dphy_reset(phy, 1); // place the digital section of D-PHY in ON state;
2). Second, configure dsi register, such as PLL, the commands transmision mode and so on.
mipi_dsih_hal_power(instance, 0); // Configure power status of DSI Host core, 1: ON; 0: OFF
mipi_dsih_hal_dpi_color_mode_pol(instance, !instance->color_mode_polarity); // Set DPI color mode pin polarity. 1: Active low; 0: Active High
mipi_dsih_hal_dpi_shut_down_pol(instance, !instance->shutdown_polarity); // DPI shutdown pin polarity. 1: Active low; 0: Active Low
mipi_dsih_hal_int_mask_0(instance, 0xffffffff);
mipi_dsih_hal_int_mask_1(instanec, 0xffffffff);
mipi_dsih_hal_phy_bta_time(instanec, instance->max_bta_cycles);
mipi_dsih_hal_dpi_lp_during_hfp(instance, 1); // By default, return to LP11 during ALL, unless specified
mipi_dsih_hal_dpi_lp_during_hbp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vactive(instance, 1);
mipi_dsih_hal_dpi_lp_during_vfp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vfp(instance, 1);
mipi_dsih_hal_dpi_lp_during_vsync(instance, 1);
mipi_dsih_hal_dcs_wr_tx_type(instance, 0, 1); // By default, all commands are sent in LP mode
mipi_dsih_hal_dcs_wr_tx_type(instance, 1, 1); // The second para is number of param
mipi_dsih_hal_dcs_wr_tx_type(instance, 3, 1); // long packet
DCS read/write commands and General read/write Commands are the same
By default, RX_VC=0, NO EOTp, EOTn, BTA, ECC rx and CRC rx.
mipi_dsih_hal_power(instance, 1); configure the core to power up;
mipi_dsih_hal_tx_escape_division(instance, 6); //Dividing by 6is aimed for max PHY frequency, 1GHz.
3). Last, call mipi+dsih_dphy_configure to configure D-PHY.
mipi_dsih_dphy_configure(&(instance->phy_instance), 1, DEFAULT_BYTE_CLOCK);
After mipi_dsih_dphy_open is called successfully, the following leds are lighten up:
TX_RXZis on
ENABLE_1 is off
LOCK is on
RSTZ is on
6.2.3. Calling mipi_dsih_dphy_configure(&p_instance->phy_instance, p_instance->max_lanes, LANE_CLOCK_FREQ); // 190MHz
Then Check if PHY_STATUS(0xB0) is 0x5.
6.2.4. If the interface is DPI, dpi should be configured as follow:
Configure number of lanes, virtual channel, video mode(burst or non burst mode), byte_clock, pixel_clock, color_coding(24bits), polarity, h_active_pixels, porch, and so on.
6.2.5. Enable rx, ecc_rx, eotp_rx, eotp_tx and send initial commands to panel in LP mode
mipi_dsih_gen_wr_cmd(p_instance, 0, init->data, init->reg & LCM_TAG_MASK); // ((1<<24) - 1)
6.2.6. Choose video mode via setting HOST_MODE_CFG register, then power down, power up DSI HOST
6.2.7. Calling mipi_dsi_enable_hs_clk will trigger that LPCLK_CTRL is wroten to 1, that is, HS clock will be enabled.
TXREQUEST_RXACTIVE_HS_CLK is ON.
6.2.8. As soon as DISPC is begun to transmit data from internal to dsi host, the following leds will be triggered.
If the lane number is 2, and lane name is 0 and 1,
TXREADY_RXACTIVE_HS_0 will be lighten up
TXREADY_RXACTIVE_HS_1 will be lighten up
6.3 dispc refresh OSD layer
DISPC base address: 0x20800000
0x004(SIZE_XY): Panel width and height. e.g. (540 * 960)
0x044(OSD_BASE_ADDRESS): base address of phyical DDR address. e.g. 0x82800000
D.LOAD "\PATH\565.raw" 0x82800000
0x048(OSD_SIZE_XY): OSD layer vertical and horizontal size. e.g. (540 * 960)
0x04c(OSD_PITCH): OSD layer pitch. It is pixel unit. e.g. 540
0x050(OSD_DISP_XY): OSD layer vertical and horizontal start position. e.g. 0x0
0x054(OSD_ALPHA): OSD layer alpha. e.g. 0xff
0x058(OSD_CK): OSD color key(R/ G/ B). e.g. 0x0
0x040(OSD_CTRL): Image layer configuration for RGB. e.g. 0x255
OSD_BLEND_MODE [BIT17:16],
OSD_RB_SWITCH [BIT15],
OSD_SWTICH [BIT9:8]: 0-{B0,B1,B2,B3}; 1-{B3,B2,B1,B0}; 2-{B2,B3,B0,B1}; 3-{B1,B0,B3,B2}
OSD_FORMAT [BIT7:4]: 0011-RGB888; 0101-RGB565
OSD_ALPHA_SEL [BIT3:2]: 0-pixel alpha; 1-block alpha; 2-combo alpha(pixel alpha * block alpha)
OSD_CK_EN BIT[1]: 1-color key enable
OSD_EN [BIT0]: 1-image layer enable
Last, set 0x80 to 0xa0, start to run dispc: set 0x0 to 0x11
6.4 dispc refresh IMG layer
0x020(IMG_CTRL): Image layer configuration for YUV e.g. 0x501
BIT[15](IMG_RB_SWITCH): 1 -> Exchange R and B; 0 -> Don't switch (Used for RGB data)
BIT[13:12](IMG_V_SWITCH): 0 - {B0, B1, B2, B3}; 1 - {B3, B2, B1, B0}; 2 - {B2, B3, B0, B1}; 3 - {B1, B0, B3, B2} (Used for YUV data)
BIT[11:10](IMG_UV_SWITCH): 0 - {B0, B1, B2, B3}; 1 - {B3, B2, B1, B0}; 2 - {B2, B3, B0, B1}; 3 - {B1, B0, B3, B2} (Used for YUV data)
BIT[9:8](IMG_Y_SWITCH): 0 - {B0, B1, B2, B3}; 1 - {B3, B2, B1, B0}; 2 - {B2, B3, B0, B1}; 3 - {B1, B0, B3, B2} (Used for YUV data)
BIT[7:4](IMG_FORMAT): 0000 - YUV422; 0001 - YUV420; 0011 - RGB888; 0101 - RGB565; 1000 - 3plane YUV422; 1001 -3plane YUV420
BIT[0](IMG_EN): 1 - Enable
0x0024: IMG_Y_BASE_ADDR
0x0028: IMG_UV_BASE_ADDR
0x002C: IMG_V_BASE_ADDR If the image format is YUV 3 plane, this address should be set.
0x0030: IMG_SIZE_XY
0x0034: IMG_PITCH It is pixel unit, e.g. 540
0x0038: IMG_DISP_XY Image layer start position. It is oftern 0x0
Last, set 0x80 to 0xa0, start to run dispc: set 0x0 to 0x11
If 0x80 is set to 0xa0, then the corresponding registers, such as: base address, background color and so on, will be set.After these registers are updated successfully, 0x80 will be set to 0x80 again. If not, maybe dpi clockisn't enabled.
7 Pack system image and boot image
packsys # pack system image packboot # pack boot image
The following commands are In android root/out/host/linux-x86/bin, such asadb, mkbootfs
aapt aprotoc checkpolicy clang-tblgen dexdeps dmtracedump hierarchyviewer1 llvm-as minigzip mkuserimg.sh sqlite3 acp bcc_strip_attr checkseapp dalvik dexdump dx hprof-conv llvm-link mkbootfs oatdump tblgen adb bsdiff clang dalvikvm dexlist e2fsck imgdiff llvm-rs-cc mkbootimg rs-spec-gen zipalign aidl checkfc clang++ dex2oat dexopt fastboot insertkeys.py make_ext4fs mksnapshot.arm simg2img
8 DDR
8.1 how to check DDR map
Add a file named dispc.scat, whose content is as following:
ROM_LOAD0 0x80000000
{
ROM_EXEC0 +0x0
{
init.o (Init, +FIRST)
* (+RO) ; code and read only data
* (+RW,+ZI) ; Read/Write variables and uninitialized variables
}
}
Add this ENTRY address to DISPC.mk, as following:
ENTRY = 0x80000000 SCATFILE = DISPC.scat TARGET = DISPC ENTRY_POINT = 0x0 LINK_SCAT = DISPC.scat
After adding these fields, we can check if the address is right, according to open generated map file: SHARKL_AP_FPGA_DISPC_test.map.
Meanwhile, SHARKL_AP_FPGA_DISPC_test.axf is generated too.
9 arm compiler used for minicode
a. ARM DS-5 ARMv8 -> Eclipse for DS-5 ARMv8
b. ARM -> ARM Workbench IDE v4.0 (It is exactly Eclipse)
-> RealView Development Suite v4.1/3.1
-> RealView Profiler v1.0
-> RealView ICE v3.2/4.1
c. Cygwin
10 General Knowledges
10.1 Chip size, chip POP(DDR+SOC)
half ram, half stardard cell
10.2 FPGA can't verify analog circuit
10.3 Wafer test is necessory. This can improve yield rate.
10.4 The way of naming arm process is odd, A53(V8 instruction set and 64-bit),A57, A9, A7(V7 instruction set and 32-bit) and so on.
11 guide for debugging android source codes(SPREADTRUM)
11.1 概念及流程介绍
bitfile：用来下载到FPGA上执行的文件。有这个文件就知道FPGA的内部链接了分内置romcode和不带romcode，如果带romcode当bitfile下载完毕时会自动跳到romcode去执行，否则需要使用trace32加载romcde
romcode：根据拨码开关判断是开机还是下载模式
下载：
romcode：与pc通信下载FDL1到IRAM，并运行FDL1
fdl1 ：初始化ddr，与pc通信下载fdl2到ddr，并运行fdl2
fdl2 : 初始化nand（emmc），与pc通信下载其它image到nand（emmc）
开机：
rocode： 判断是开机，复制spl到IRAM, 并运行spl
SPL ： 初始化ddr，复制u-boot到ddr，并运行u-boot
u-boot： 部分设备初始化，复制其它的iamge到ddr，判断开机模式进入相应模式
11.2 基本环境搭建
fpga 需要的相关文件在内网已共享：bit： 请根据是ddr1还是ddr2分别选择相应的bitfile文件
img： android相关的image
tools： HSDL SecureCRT download tools
cmms： trace32 脚本文件
11.3 注意事项
11.3.1 bitfile分ddr1和的ddr2，带romcode或者不带，请确认是否选择正确11.3.2 ddr1需要使用1.8v电压，ddr2是1.2v，需要调整拨码开关
11.3.3 download android source code(shanghai)
repo init -u [email protected]:android/platform/manifest.git -b sprdroid4.4_3.10_sharkl_dev [email protected]:tools/newrepo.git
11.3.4 compilation error
make: *** No rule to make target 'init.s', needed by 'init.o', stop
This error is often caused by the wrong file name or the wrong file directory.
12 mipi burst and non burst mode of synopsis
12.1 Burst Mode
In this mode, the entire active pixel line is buffered into a FIFO and transmitted in a single packet with no interruptions. This transmission mode requires that the DPI Pixel FIFO has the capacity to store a full line of active pixel data inside it.This mode is optimally used if the difference between the pixel required bandwidth and DSI link bandwidth is very different. This enables the DWC_mipi_dsi_host to quicky dispatch the entire video line in a single burst of data and then return to low-power mode.
12.2 Non-Burst Mode
In this mode, the processor uses the partitioning properties of the DWC_mipi_dsi_host to divide the video line thansmission into several DSI packets. This is done to match the pixle required bandwidth with the DSI link bandwidth. With this mode, the controller configuration does not require a full line of pixel data to be stored inside the DPI Pixel FIFO. It requires only the content of one video packet.
12.3 Guidelines for Selecting the Burst or Non-Burst Mode
Selecting the Burst and Non-Burst mode is mainly dependent on the system configuration and the device requirements. Choose the video transmission mode that suits the application scenario. The Burst mode is more beneficial because it increases the probability of the link spending more time in the low-power mode, decreasing power consumption. However, the following conditions should be met for availing(有益于) the maximum benefits from the Burst mode of operation:
1. The DWC_mipi_dsi_host core should have sufficient pixel memory to store an entire pixel line to avoid the overflow of the internal FIFOs.
2. The display device should support receiving a full pixel line in a single packet burst to avoid the overflow on the reception buffer.
3. The DSI output bandwidth should be higher than the DPI system interface input bandwidth in a relation that enables the link to go to low-power once per line.
If the system cannot meet these requirements, it is likely that the pixel data will be lost causing the malfunctioning of the display device while using the Burst mode. These errors are related to the capabilities of the system to store the temporary pixel data.
If all the conditions for using the Burst mode cannot be met, use the Non-Burst mode to avoid the errors caused by the Burst mode. The Non-Burst mode provides a better matching of rates for pixel transmission, enabling:
1. Only a certain amount of pixels to be stored in the memory and not requiring a full pixel line (lesser DPI RAM requirements in the DWC_mipi_dsi_host)
2. Operation with devices that support only a small amount of pixel buffering (less than a full pixel line)
The DSI Non-Burst mode should be configured in such way that the DSI output pixel ratio matches with the DPI input pixel ratio, reducing the memory requirements on both dsi host and/or device side. This is achieved by dividing a pixel line into several chunks of pixels and optionally interleaving them with null packets.
The folling equations show how the DWC_mipi_dsi_host core transmission parameters should be programmed in Non-Burst mode to match the DSI link pixel output ration (left hand side of the "=" sign) and DPI pixel input (right hand side of the "=" sign).
When the null packets are enabled:
lanebyteclkperiod * vid_num_chunks (vid_pkt_size * bytes_per_pixel + 12 + vid_null_size) / number_of_lanes = pixels_per_lines * dpipclkperiod
When the null packets are disabled:
lanebyteclkperiod * vid_num_chunks (vid_pkt_size * bytes_per_pixel + 6) / number_of_lanes = pixels_per_lines * dpipclkperiod
12.4 Config Burst mode and Non-Burst mode
a. Burst Mode
VID_MODE_CFG[vid_mode_type] = 0x2'b1x
VID_PKT_SIZE[vid_pkt_size] = sizeof(active line period, measured in pixels)
vid_num_chunks and vid_null_size are ignored by the DWC_mipi_dsi_host
b. Non-Burst mode
VID_MODE_CFG[vid_mode_type] = 2'b0x
VID_MODE_CFG[vid_mode_type] = 2'b00 to enable the transmission of sync pulses
VID_MODE_CFG[vid_mode_type] = 2'b01 to enable the transmission of sync events
VID_MODE_CFG[vid_pkt_size] = the number of pixels to be transmitted in a single packet
VID_NUM_CHUNKS[vid_num_chunks] = the number of packets to be transmitted per video line. The value of vid_pkt_size * vid_num_chunks is the number of pixels per line of video, except if vid_num_chunks is 0, which disables the multi-packets. If you set it to 1, there is still only one packet per line, but it can be part of a chunk, followed by a null packet.
VID_NULL_SIZE[vid_null_size] = the size of null packets to be inserted as part of the chunks. Setting it to 0 to disables null packets.
13 scat
a. dispc.scat 64bit
ROM_LOAD0 0x80000000
{
ROM_EXEC0 +0x0
{
init.o (BOOT, +FIRST)
* (+RO, +RW, +ZI)
}
; app stack and heap must be 128-byte aligned
ARM_LIB_STACKHEAP +0 ALIGN 128 EMPTY 0x10000000 {}
}
makefile
# TSHARKL64_AP_FPGA.mk COMPILER = DS-5_64BIT ifeq ($(strip $(COMPILER)), DS-5_64BIT) MINCPATH += inc/common/DS-5_64bit else MINCPATH += inc/common/DS-5_32bit endif # makefile TARGET_CPU = 8-A.64 Q = AR="$PATH/DS-5 ARMv8/bin/armar" AR="$PATH/DS-5 ARMv8/bin/armasm" AR="$PATH/DS-5 ARMv8/bin/armcc" AR="$PATH/DS-5 ARMv8/bin/armlink" AR="$PATH/DS-5 ARMv8/bin/fromelf"
# DISPC.mk ifeq ($(strip (COMPILER)), DS-5_64BIT) ENTRY = 0x800000000 SCF_PATH = DS-5_64bit else ENTRY = 0x800000000 SCF_PATH = DS-5_32bit endif SCATFILE = $(SCF_PATH)/DISPC.scat DSI_SRC_FILE = ... DISPLAY_SRC_FILE = ... MINCPATH += inc ... MSRCPATH += modules/DISPC ... SOURCES += init.s \ isr_vec.s \ handle.s \ arm_isr.s \ main.c \ $(DISPLAY_SRC_FILE)
b. dispc.scat 32bit
ROM_LOAD0 0x80000000
{
ROM_EXEC0 +0x0
{
init.o (Init, +First)
* (+RO, +RW, +ZI)
}
}
ROM_LOAD1 0x00000000
{
ROM_EXEC1 +0x0
{
isr_vec.o (Vector, +First)
}
}
14 bringup sharkl FPGA
-rw-r--r-- 1 1314 Mar 20 16:21 Android.mk drwxr-xr-x 5 4096 Mar 20 16:21 driver/ -rw-r--r-- 1 428 Apr 3 16:10 egl.cfg -rw-r--r-- 1 388 Mar 20 16:21 libboost.so -rwxr-xr-x 1 13348 Mar 20 16:21 libEGL_mali.so* -rwxr-xr-x 1 25644 Mar 20 16:21 libGLESv1_CM_mali.so* -rwxr-xr-x 1 21544 Mar 20 16:21 libGLESv2_mali.so* -rwxr-xr-x 1 1070552 Mar 20 16:21 libMali.so* drwxr-xr-x 3 4096 Mar 20 16:21 src/ drwxr-xr-x 2 4096 Mar 20 16:21 tools/
And egl.cfg can be edited, such as
0 0 android #0 1 mali
And BoardConfigCommon.mk should be modified, as following
diff --git a/scx35/BoardConfigCommon.mk b/scx35/BoardConfigCommon.mk index 428ae05..598fc74 100644 --- a/scx35/BoardConfigCommon.mk +++ b/scx35/BoardConfigCommon.mk @@ -73,9 +73,9 @@ USE_BOOT_AT_DIAG := true # graphics TARGET_GPU_PP_CORE := 2 -USE_SPRD_HWCOMPOSER := true -USE_OPENGL_RENDERER := true -USE_OVERLAY_COMPOSER_GPU := true +USE_SPRD_HWCOMPOSER := false +USE_OPENGL_RENDERER := false +USE_OVERLAY_COMPOSER_GPU := false # ota TARGET_RELEASETOOLS_EXTENSIONS := vendor/sprd/open-source/tools/ota
And device.mk should be modified
diff --git a/scx35/device.mk b/scx35/device.mk
index 20a9c2c..700861c 100644
--- a/scx35/device.mk
+++ b/scx35/device.mk
@@ -14,8 +14,7 @@ PRODUCT_PACKAGES += \
libGLESv1_CM_mali.so \
libGLESv2_mali.so \
libMali.so \
- libboost.so \
- mali.ko
+ libboost.so
# video modules
PRODUCT_PACKAGES += \
And init.sc9930.rc should be modified
diff --git a/scx35/init.sc8830.rc b/scx35/init.sc8830.rc
index ceb4edb..cf9d63c 100644
--- a/scx35/init.sc8830.rc
+++ b/scx35/init.sc8830.rc
@@ -46,7 +46,7 @@ on fs
on post-fs
chown system system /productinfo
chmod 0774 /productinfo
- insmod /system/lib/modules/mali.ko
+# insmod /system/lib/modules/mali.ko
insmod /system/lib/modules/trout_fm.ko
on post-fs-data
And init.board.rc should be modified
diff --git a/scx35l_sp9630fpga/init.board.rc b/scx35l_sp9630fpga/init.board.rc
index dd02dd1..20c4350 100644
--- a/scx35l_sp9630fpga/init.board.rc
+++ b/scx35l_sp9630fpga/init.board.rc
@@ -38,6 +38,7 @@ on boot
mkdir /data/misc/dhcp 0770 dhcp dhcp
chown dhcp dhcp /data/misc/dhcp
setprop wifi.interface wlan0
+ setprop ro.kernel.qemu 1
mkdir /data/cg/ 0777 system system
mkdir /data/cg/online 0777 system system
And system.prop should be modified
diff --git a/scx35l_sp9630fpga/system.prop b/scx35l_sp9630fpga/system.prop index f03227e..ba523b3 100644 --- a/scx35l_sp9630fpga/system.prop +++ b/scx35l_sp9630fpga/system.prop @@ -1,7 +1,7 @@ ro.sf.lcd_density=240 -ro.sf.lcd_width=54 -ro.sf.lcd_height=96 +ro.sf.lcd_width=102 +ro.sf.lcd_height=60 ro.opengles.version=131072 ro.product.hardware=SP9630FPGA_V1.0.1
And ION should be used in kernel_config, such as CONFIG_ION, CONFIG_ION_SPRD, CONFIG_FB, and so on.
15 synopsis lp2hs and hs2lp time adjusting
15.1 DSI HOST
0x09C - PHY_TMR_CFG This register sets the time that the DWC_mipi_dsi_host assumes in calculations for the data lanes to switch between high-speed and low-power.
[31:24] - phy_hs2lp_time Maximum time that D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles
[23:16] - phy_lp2hs_time Maximum time that D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles
[15] - reserved
[14:0] - max_rd_time This field configures the maximum time required to perform a read command in lane byte clock cycles.
15.2 D-PHY
0x22 - AFE/BIAS/Bandgap Analog Programmability
This test code controls the various parameters in the DWC MIPI D-PHY Bidir 4L.
BIT 7: Program selector
0 - Set 0 is programmed 11'bxxxx0000000
1 - Set 1 is programmed 11'b0000xxxxxxx
BITs 6...0: Analog programmability
10 - 1.5Gbps support
9:7
6
5:3: Adjust LP TX bias current
2:0
data[0] = 0x8B; mipi_dsih_dphy_write(phy, 0x22, data, 1); data[0] = 0x3B; // data[0] = 0x38; // increase LP TX bias current to 166.7% // data[0] = 0x1B; // increase LP TX bias current to 100% mipi_dsih_dphy_write(phy, 0x22, data, 1);
/**
* Write to D-PHY module (encapsulating the digital interface)
* @param instance pointer to structure which holds information about the d-phy
* module
* @param address offset inside the D-PHY digital interface
* @param data array of bytes to be written to D-PHY
* @param data_length of the data array
*/
void mipi_dsih_dphy_write(dphy_t * instance, uint8_t address, uint8_t * data, uint8_t data_length)
{
unsigned i = 0;
if (data != 0)
{
#if ((defined DWC_MIPI_DPHY_BIDIR_TSMC40LP) || (defined DPHY2Btql) || (defined GEN_2))
/* set the TESTCLK input high in preparation to latch in the desired test mode */
mipi_dsih_dphy_test_clock(instance, 1);
/* set the desired test code in the input 8-bit bus TESTDIN[7:0] */
mipi_dsih_dphy_test_data_in(instance, address);
/* set TESTEN input high */
mipi_dsih_dphy_test_en(instance, 1);
/* drive the TESTCLK input low; the falling edge captures the chosen test code into the transceiver */
mipi_dsih_dphy_test_clock(instance, 0);
/* set TESTEN input low to disable further test mode code latching */
mipi_dsih_dphy_test_en(instance, 0);
/* start writing MSB first */
for (i = data_length; i > 0; i--)
{
/* set TESTDIN[7:0] to the desired test data appropriate to the chosen test mode */
mipi_dsih_dphy_test_data_in(instance, data[i - 1]);
/* pulse TESTCLK high to capture this test data into the macrocell; repeat these two steps as necessary */
mipi_dsih_dphy_test_clock(instance, 1);
mipi_dsih_dphy_test_clock(instance, 0);
}
#endif
}
}
/* for all Gen2 testchips, bypass LP TX enable idle low power (save power consumption) */
data[0] = 0x80;
mipi_dsih_dphy_write(phy, 0x32, data, 1);
mipi_dsih_dphy_write(phy, 0x42, data, 1);
mipi_dsih_dphy_write(phy, 0x52, data, 1);
mipi_dsih_dphy_write(phy, 0x82, data, 1);
mipi_dsih_dphy_write(phy, 0x92, data, 1);
/* 0x03: HS request(LP01), actual: about 45ns * 0x04: actual: about 51ns * 0x1f: bigger than 512ns */ data[0] = 0x9f; mipi_dsih_dphy_write(phy, 0x60, data, 1); mipi_dsih_dphy_write(phy, 0x70, data, 1); /* 0x26: HS-EXIT = Treot + LP11, actual: Treot 39ns, LP11 is too long */ /* 0x23: Treot = 40ns */ /* 0x21: Treot = 35ns */ data[0] = 0x21; mipi_dsih_dphy_write(phy, 0x64, data, 1); mipi_dsih_dphy_write(phy, 0x74, data, 1);
0x60 - 0x65
0x70 - 0x75
-
1. TREOT Fail
-
a. The measurement will be performed using the ZID = 100 ohms termination case only, so please check.
b. Please modify testcode 0x22 Analog programmability[10:0] to the following values:
-
[10]: 0 for PLL speed lower than 1G; 1 for PLL speed larger than 1G;
[9:7]: 011 - 100%
[6]: 0 - 100%
[5:3]: 011 - 100%
[2:0]: 011 - 100%
-
c. Please check if the common mode capacitor Ccm is 47pf.
-
2. VCMTX(LF) Fail
-
a. The measurement will be performed using the ZID = 100 ohms termination case only, so please check.
b. Please check if the common mode capacitor is connected properly and the common mode capacitor Ccm is 47pf.
c. Please check if a 8th-order Butterworth IIR bandpass filter is used as the test filter, with –3dB cutoff frequencies of 50 and 450MHz.
d. Please check if the DPHY receiver is as the attached file "DPHY_Receiver_Termination.pdf".
e. Since the results of VCMTX test are not stable, could you please check if the test fixture setup is not stable, and could you please provide a photo of your setup?
4. Could you please provide the raw data of one complete Burst using the maximum memory depth of the scope to get the maximum duration and keep the sampling rate (resolution) around 12.5GS/s.
-
Attached file "extractwaveforms.pdf" is a guideline on how to export the waveforms(.bin format).
These should be captured with differential probes. The captures of interest are:
- CLK_P, CLK_N
Just a remark that all the data measurement should be done single ended with clean ground.
16 user space transfer parameters to kernel space
static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
{
if (access_ok(VERIFY_READ, from, n))
n = __copy_from_user(to, from, n);
else /* security hole - plug it */
memset(to, 0, n);
return n;
}
static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n)
{
if (access_ok(VERIFY_WRITE, to, n))
n = __copy_to_user(to, from, n);
return n;
}
These functions will ensure that the corresponding pointer is within right range( kernel: >= 0xc0000000; userspace: <= 0xc0000000), meanwhile, what pointer points to can be identified. So if these contents is modified by userspace again, the abnormal behavior won't happen. The following system.map comes from vmlinux.
1 00000000 t __vectors_start
2 00000020 A cpu_v7_suspend_size
3 00001000 t __stubs_start
4 00001004 t vector_rst
5 00001020 t vector_irq
6 000010a0 t vector_dabt
7 00001120 t vector_pabt
8 000011a0 t vector_und
9 00001220 t vector_addrexcptn
10 00001224 t vector_fiq
11 00001224 T vector_fiq_offset
12 c0004000 A swapper_pg_dir
13 c0008000 T _text
14 c0008000 T stext
15 c000807c t __create_page_tables
16 c0008154 t __turn_mmu_on_loc
17 c0008160 t __vet_atags
18 c0009000 T __exception_text_start
19 c0009000 T _stext
20 c0009000 T asm_do_IRQ
21 c0009004 T do_undefinstr
22 c0009154 T do_IPI
23 c0009158 T do_DataAbort
24 c00091f0 T do_PrefetchAbort
25 c0009288 t gic_handle_irq
26 c00093ec T __exception_text_end
27 c00093f0 t __do_fixup_smp_on_up
28 c0009404 T fixup_smp
29 c000941c t do_one_initcall_debug
30 c00094c8 t run_init_process
31 c00094dc T do_one_initcall
32 c0009598 t match_dev_by_uuid
33 c00095c8 T name_to_dev_t
34 c000995c t vfp_force_reload
35 c00099a0 t vfp_raise_sigfpe
36 c0009a10 t vfp_enable
37 c0009a4c t vfp_cpu_pm_notifier
38 c0009af0 t vfp_hotplug
39 c0009b30 t vfp_emulate_instruction.isra.2
40 c0009bac t vfp_raise_exceptions
41 c0009d18 T VFP_bounce
42 c0009e3c T vfp_sync_hwstate
43 c0009ec4 t vfp_notifier
44 c000a024 T vfp_flush_hwstate
45 c000a06c T vfp_preserve_user_clear_hwstate
46 c000a0f8 T vfp_restore_user_hwstate
47 c000a16c T do_vfp
48 c000a188 T vfp_null_entry
17 Compilation problem
# kheader
# make -j4
# make systemimage -j4 # make recoveryimage -j4 # make bootimage -j4 # make bootloader -j4 # make chipram -j4
and so on.
17.2 Compile kernel separately, issue the following command:
# kmk -j 4
18 Enable/Disable kernel log output
CONFIG_DEBUG_LL=y CONFIG_DEFAULT_MESSAGE_LOGLEVEL=7disable:
如果你运气不太好，那么第一次启动kernel，最多看见: uncompressing linux...ok, booting the kernel
从串口ttyS0出来，然后你什么都没了。这总情况遇见的机会还是很多的。多数原因是内核卡住了。你可能会问，内核卡住了不要紧呀，至少没卡住的代码中的printk应该可以出来。你这样想，那就是你还没有读过printk的代码。 在串口驱动初始话前的printk语句是不会即时的打出，而是存在内存中，然后等串口初始化完毕，这些message一下就冲了出来。 问题是如果在串口初始化完毕之前，内核卡住，那么你就什么message也看不见. 因此，问题就是解决这个即时打印的问题，linux kernel其实提供了这套机制，它的相关代码用 CONFIG_DEBUG_LL 包裹着。 一旦被打开，那么printk就会call printascii()函数。printacii是汇编语言写成，在kernel/arch/arm/kernel/debug.S有定义.它不做实质的动作，主要判断string的结束。这个函数会call几个函数: addruart, waituart, senduart, busyuart . 这些函数要求由汇编写成，并且和体系结构相关，一般都一定在下面的文件里 kernel/arch/arm/mach-xxx/include/mach/debug-macro.S 而且这个文件不会被单独编译，他其实就被包含在kernel/arch/arm/kernel/debug.S中： #include <mach/debug-macro.S> 打开CONFIG_DEBUG_LL这个标志以后，你就可以得到即时debug message了
-------以上内容转自：http://blog.csdn.net/cpuwolf/article/details/4492822-------
以下是关于如何打开内核的low level debug 配置
make menuconfig ---> Kernel hacking ---> 选中：Kernel debugging。
当选中Kernel debugging后，才能看见Kernel low-level debugging functions. 选中即可。
Using putty on ubuntu
$ sudo puttyChoose /dev/ttyUSB1, 115200
Choose Window: lines of scrollback : 50000; column: 120; row: 40; fonts: client:Courier New 12; Default foreground: [255, 255, 255]
19 dispc referenced clock
// SharkL only support mipi and lvds interface and sharkl has only one dispc, so there is no dispc1.
// 1.
SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1),
REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0)|BIT(1),
4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m);
// name: "clk_disc0";
// current clk referenced source: clk_256m
// 2.
SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1),
REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1),
4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m);
// name: "clk_disc0_dbi"
// current clk referenced source: clk_256m
// 3.
SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1),
REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1),
4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m);
// name: "clk_disc0_dpi"
// current clk referenced source: clk_384m
// 4.
SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11),
0, 0, 0, 0,
1, &clk_aon_apb);
// name: "clk_disp_emc"
// current clk referenced source: clk_aon_apb
clk_384m: clk_384m {
compatible = "sprd,fixed-factor-clock";
#clock-cells = <0>;
clock-mult = <1>;
clock-div = <2>;
clocks = <&clk_tdpll>;
clock-output-names = "clk_384m";
};
clk_256m: clk_256m {
compatible = "sprd,fixed-factor-clock";
#clock-cells = <0>;
clock-mult = <1>;
clock-div = <3>;
clocks = <&clk_tdpll>;
clock-output-names = "clk_256m";
};
clk_192m: clk_192m {
compatible = "sprd,fixed-factor-clock";
#clock-cells = <0>;
clock-mult = <1>;
clock-div = <4>;
clocks = <&clk_tdpll>;
clock-output-names = "clk_192m";
};
clk_aon_apb: clk_aon_apb {
compatible = "sprd,composite-dev-clock";
#clock-cells = <0>;
reg = <0x402d0028 0x3 0x402d0028 0x300>; /* select reg and divider reg */
clocks = <&ext_26m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>;
clock-output-names = "clk_aon_apb";
};
clk_disp_emc: clk_disp_emc {
compatible = "sprd,gate-clock";
#clock-cells = <0>;
reg = <0x402e0004 0x800>; /* enable reg */
clocks = <&clk_aon_apb>;
clock-output-names = "clk_disp_emc";
};
ext_26m: ext_26m {
compatible = "sprd,fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "ext_26m";
};
ext_32k: ext_32k {
compatible = "sprd,fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ext_32k";
};
clk_mpll: clk_mpll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e3070 0x7ff 0x402b0094 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_mpll";
};
clk_dpll: clk_dpll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e3074 0x7ff 0x402b0098 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_dpll";
};
clk_tdpll: clk_tdpll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e3078 0x7ff 0x402b009c 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_tdpll";
};
clk_wpll: clk_wpll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e301c 0x7ff 0x402b00a0 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_wpll";
};
clk_cpll: clk_cpll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e307c 0x7ff 0x402b00a4 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_cpll";
};
clk_wifipll: clk_wifipll {
compatible = "sprd,adjustable-pll-clock";
#clock-cells = <0>;
reg = <0x402e3080 0x7ff 0x402b00a8 0x1>; /* mult reg and prepare reg */
clock-output-names = "clk_wifipll";
};
20 Compile kernel separately
cd ~/bin
wget http://releases.linaro.org/14.01/components/toolchain/binaries/gcc-linaro-aarch64-linux-gnu-4.8-2014.01_linux.tar.xz
tar xf gcc-linaro-aarch64-linux-gnu-4.8-2014.01_linux.tar.xz
PATH=$PATH:~/bin/gcc-linaro-aarch64-linux-gnu-4.8-2014.01_linux/bin
二、kernel代码分支切换到64bit
cd kernel/
git fetch --all
git checkout -b ...
三、更新open source branch: sprdroid4.4_3.10_sharkl_dev
cd vendor/.../open-source/
git fetch --all
git checkout -b ...
五、获取ramfs，ramfs.tar.bz2参见附件
sudo tar -xjf ramfs.tar.bz2
cd ramfs
pwd
...
六、编译kernel
export PATH=$PATH:~/bin/gcc-linaro-aarch64-linux-gnu-4.8-2014.01_linux/bin （64位Toolchain 地址）
export CROSS_COMPILE=aarch64-linux-gnu-
export ARCH=arm64
cd kernel
make ARCH=arm64 ..._defconfig
在编译前，需要修 改.config文件
gedit .config
CONFIG_INITRAMFS_SOURCE="/home/.../ramfs"（ramfs 地址）
make -j4
如编译ok，生成 ../kernel/arch/arm64/boot/Image
七、由于暂时没有uboot，需要使用boot wrapper将Image做成axf文件
cd vendor/sprd/open-source/tools/boot-wrapper-aarch64
./build.sh
编译得到 ../vendor/sprd/open-source/tools/boot-wrapper-aarch64/linux-system.axf，即可load到FPGA的DDR2上运行。
正常运行的结果是可以在串口工具中跑进kernel。
目前这套kernel代码以及FPGA验证环境是单核（mp1）的。