NXP TPMS LF PROTOCL GENERATER_SOURCE CODE

`timescale 10ns / 10ns

module LFOutput (
clk, rstin,data,
LED
);

input clk;
input rstin;
output data;

output LED;

wire clk;
wire rstin;
wire data;

wire rst = ~rstin;

wire LED = rst;

//******************************************************************
//Make the counter to generate flag for DClk (TFPGA = 12500TBIT)
//******************************************************************
reg[13:0] cnt;
wire flag_cnt = cnt[13];

always @ ( posedge clk )
begin
    if (!rst)
    cnt <= 14'h186A;
    else
    begin
        if (flag_cnt)
        cnt <= 14'h186A;
        else
        cnt <= cnt-1;
    end
end

//***************************************************
//Generate TBIT CLK
//***************************************************
reg DClk;

always @ ( posedge flag_cnt or negedge rst )
begin
    if(!rst)
    DClk <= 1;
    else
    DClk <= ~DClk;
end    

//***********************************************
//Generate DClk_div2
//***********************************************
reg div2;

always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    div2 <= 1;
    else
    div2 <= ~div2;
end



//*************************************************
//Generate Preamble Signal (17 TBIT = 4.25ms)
//*************************************************
reg[5:0] PCnt;
reg PreLine;
wire PreLine_flag = PCnt[5];

always @ ( negedge DClk or negedge rst )
begin
    if(!rst) 
    begin
        PCnt <= 6'h11;
    end
    else 
    begin
        if( PreLine_flag )
        begin
            PCnt <= 6'h11;
        end
        else
        PCnt <= PCnt - 1;
    end
end
        
always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    PreLine <= 1;
    else
    begin
        if(PreLine_flag)
        PreLine <= 0;
        else
        PreLine <= PreLine;
    end
end

wire Preamble = DClk & PreLine;

//************************************************************
//Synchronization DIV1.5 Signal (1cycle = 3 TDClk)
//************************************************************

//---------------------------------------------------------------------------
//use clk to generate DivLine1 which is one of DIV1.5 combinationa signal
//---------------------------------------------------------------------------
reg[18:0] DivCnt;
reg DivLine1;
wire DivLine1_flag = DivCnt[18];      //use counter to locate DIV1.5

always @ ( posedge clk or negedge rst )
begin
    if(!rst) 
    begin
        DivCnt <= 19'h3B826;
    end
    else 
    begin
        if( DivLine1_flag )
        begin
            DivCnt <= 19'h3B826;
        end
        else
        DivCnt <= DivCnt - 1;
    end
end
        
always @ ( posedge clk or negedge rst )
begin
    if(!rst)
    DivLine1 <= 1;
    else
    begin
        if(DivLine1_flag)
        DivLine1 <= 0;
        else
        DivLine1 <= DivLine1;
    end
end


//---------------------------------------------------------------------------
//use clk to generate SDiv3Line which is another DIV1.5 combinationa signal
//---------------------------------------------------------------------------

reg SDiv3Line;
reg[19:0] SDiv3Cnt;
wire SDiv3Cnt_flag = SDiv3Cnt[19];        //use counter to locate DIV1.5

always @ ( posedge clk or negedge rst )
begin
    if(!rst) 
    begin
        SDiv3Cnt <= 20'h40164;
    end
    else 
    begin
        if( SDiv3Cnt_flag )
        begin
            SDiv3Cnt <= 20'h40164;
        end
        else
        SDiv3Cnt <= SDiv3Cnt - 1;
    end
end
        
always @ ( posedge clk or negedge rst )
begin
    if(!rst)
    SDiv3Line <= 1;
    else
    begin
        if(SDiv3Cnt_flag)
        SDiv3Line <= 0;
        else
        SDiv3Line <= SDiv3Line;
    end
end 

//---------------------------------------------------------
//Combinate the synchronization DIV1.5 signal
//---------------------------------------------------------

wire SDiv3Pos = DivLine1 ^ PreLine;      //SDiv3Pos is synchronization DIV1.5 Signal


//******************************************
//Synchronization DClk1 (1cycle= 1 TDClk)
//******************************************
reg SDClk1Line;
reg[5:0] SDClk1Cnt;
wire SDClk1Cnt_flag = SDClk1Cnt[5];

always @ ( negedge DClk or negedge rst )
begin
    if(!rst) 
    begin
        SDClk1Cnt <= 6'h15;
    end
    else 
    begin
        if( SDClk1Cnt_flag )
        begin
            SDClk1Cnt <= 6'h15;
        end
        else
        SDClk1Cnt <= SDClk1Cnt - 1;
    end
end
        
always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    SDClk1Line <= 1;
    else
    begin
        if(SDClk1Cnt_flag)
        SDClk1Line <= 0;
        else
        SDClk1Line <= SDClk1Line;
    end
end 

wire SDClk1Pos = SDClk1Line ^ SDiv3Line;
wire SDClk1 = DClk & SDClk1Pos;


//********************************************
//Synchronization div2 (1cycle = 2 TDClk)
//********************************************
//reg SDiv3Line;
reg SDiv2Line;
//reg[5:0] SDiv3Cnt;
reg [5:0] SDiv2Cnt;
//wire SDiv3Cnt_flag = SDiv3Cnt[5];
wire SDiv2Cnt_flag = SDiv2Cnt[5];

always @ ( negedge DClk or negedge rst )
begin
    if(!rst) 
    begin
        SDiv2Cnt <= 6'h19;
    end
    else 
    begin
        if( SDiv2Cnt_flag )
        begin
            SDiv2Cnt <= 6'h19;
        end
        else
        SDiv2Cnt <= SDiv2Cnt - 1;
    end
end
        
always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    SDiv2Line <= 1;
    else
    begin
        if(SDiv2Cnt_flag)
        SDiv2Line <= 0;
        else
        SDiv2Line <= SDiv2Line;
    end
end 

wire SDiv2Pos = SDiv2Line ^ SDClk1Line;
wire SDiv2 = div2 & SDiv2Pos;

//******************************************
//Synchronization DClk2 (1cycle = 1 TDClk)
//******************************************
reg SDClk2Line;
reg[5:0] SDClk2Cnt;
wire SDClk2Cnt_flag = SDClk2Cnt[5];

always @ ( negedge DClk or negedge rst )
begin
    if(!rst) 
    begin
        SDClk2Cnt <= 6'h1A;
    end
    else 
    begin
        if( SDClk2Cnt_flag )
        begin
            SDClk2Cnt <= 6'h1A;
        end
        else
        SDClk2Cnt <= SDClk2Cnt - 1;
    end
end
        
always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    SDClk2Line <= 1;
    else
    begin
        if(SDClk2Cnt_flag)
        SDClk2Line <= 0;
        else
        SDClk2Line <= SDClk2Line;
    end
end 

wire SDClk2Pos = SDClk2Line ^ SDiv2Line;
wire SDClk2 = DClk & SDClk2Pos;

//**********************************************************
//LF Protocol Signal
//**********************************************************

wire PtoSig = Preamble | SDiv3Pos | SDClk1 | SDiv2 | SDClk2;


//*************************************************
//Wakeup ID & Data
//*************************************************
//reg SDClk2Line;
reg DataLine;
//reg[5:0] SDClk2Cnt;
reg [5:0] DataCnt;
//wire SDClk2Cnt_flag = SDClk2Cnt[5];
wire DataCnt_flag = DataCnt[5];

always @ ( negedge DClk or negedge rst )
begin
    if(!rst) 
    begin
        DataCnt <= 6'h1A;
    end
    else 
    begin
        if( DataCnt_flag )
        begin
            DataCnt <= 6'h1A;
        end
        else
        DataCnt <= DataCnt - 1;
    end
end
        
always @ ( posedge DClk or negedge rst )
begin
    if(!rst)
    DataLine <= 0;
    else
    begin
        if(DataCnt_flag)
        DataLine <= 1;
        else
        DataLine <= DataLine;
    end
end

wire WData = DClk & DataLine;


//**************************************
//data output
//**************************************

assign data = PtoSig | WData;


endmodule