【HDLBits习题详解 2】Circuit - Sequential Logic(5)Finite State Machines 【更新中...】
1.Fsm1(SimpleFSM1-asynchronousreset)moduletop_module#(parameterA=0;parameterB=1;),(outputregout,inputclk,inputareset,inputin);regstate,next_state;//Outputlogic//assignout=(state==...);assignout=;alway