FPGA关于时序报告的问题

 项目上用了LATTICE 的ECP3-35做视频处理相关的， 因为资源利用率比较高。

用了 185MHZ时钟去读写DDR1， 很难通过时序。ddr的时钟总是缺少一些。因为当时项目周期短，然后就一直用在项目现场上， 后来发现在板子运行几天之后，会出现DDR读写错误。和 技术支持讨论了下， 有可能是 时序的问题。

费了老大劲，终于跑到了185MHZ//// 撒花。。。。。

我还要继续测试。。

关于lattice 官方给的一些建议：

If the designis routable and achieved timing

1. Check preferences’ accuracy
2.Check if coverage is enough

3.Use the timing closure techniquesto build margin

If the designis routable but did not achieve timing

1. Relax design goals (preference values) ifpossible

2. Add relaxation preferences(BLOCK, MULTICYCLE)

3. Always - check constraint coverage( eg clock domain transfer)

4. Check potential timing preference“traps”

5. Tune RTL

6. Multiple PAR run

Ifthe designis not routable

1. Relax constraint in Synthesis

2. Reduce number of signal and number of connections

关于代码风格书写：

1.Shift register not using distributed RAM

2. BlockRAM related designs use the output register

3. State machine encoding

4. DSPrelated function use all three registers

5. Obvious register/pipelining opportunity

HDL changes to consider later

1. I/Otiming, to use or not to use I/O registers
2.Clock enable implementation

3. Manual f anout control

4. DSPblock used to implement none arithmetic functions (ECP3)