FPGA2016~2018，FPL2017会议论文整理（持续更新）

     

目录                     

                                        FPGA2016会议论文

                                        FPGA2017会议论文

                                        FPGA2018会议论文

                                        FPL2017会议论文

论文整理打包链接：https://pan.baidu.com/s/1e_C3m-A0sgXfUUNtmCTpJA，提取码：8owl    

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                                          FPGA2016会议论文

论文下载地址：https://dl.acm.org/citation.cfm?id=2847263&picked=prox   

Workshop on Overlay Architectures for FPGAFPGA    覆盖架构研讨会

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1. Hayden Kwok-Hay So, John Wawrzynek:

OLAF'16: Second International Workshop on Overlay Architectures for FPGAs.1

Designers' Day Session 1:Hardware Features 设计师日会议1：硬件功能

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1. Gregg Baeckler:

HyperPipelining of High-Speed Interface Logic.2

1. Pankaj Shanker:

Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs.3

Designers' Day Session 2:System Level Methodology  设计师日第二场：系统级方法

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1. Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo:

SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC.4

1. Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:

FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler.5-14

1. Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger:

Agile Co-Design for a Reconfigurable Datacenter.15

Technical Session 1:Neural Networks and OpenCL   技术会议1：神经网络和OpenCL

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1. Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.16-25

1. Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang, Huazhong Yang:

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.26-35

1. Bingzhe Li, M. Hassan Najafi, David J. Lilja:

Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier.36-41

1. Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu:

A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical Applications.42-47

1. Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides:

A Case for Work-stealing on FPGAs with OpenCL Atomics.48-53

Technical Session 2:Cooling and Clocking 技术会议2：冷却和时钟

----------------------------------------------------------------------------------------------------------------------

1. Zhiyuan Yang, Ankur Srivastava:

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling.54-63

1. Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:

Stratix™ 10 High Performance Routable Clock Networks.64-73

1. Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani:

Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network.74-79

Technical Session 3:Circuit Design, Graph Processing Applications 技术会议3：电路设计，图形处理应用

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1. Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.80-89

1. Safeen Huda, Jason Anderson:

Towards PVT-Tolerant Glitch-Free Operation in FPGAs.90-99

1. Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon:

Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement.100-104

1. Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang:

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.105-110

1. Tayo Oguntebi, Kunle Olukotun:

GraphOps: A Dataflow Library for Graph Analytics Acceleration.111-117

Technical Session 4:Applications and System-level Tools 技术会议4：应用和系统级工具

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1. Nikolaos Alachiotis, Gabriel Weisz:

High Performance Linkage Disequilibrium: FPGAs Hold the Key.118-127

1. Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:

LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning.128-137

1. Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou:

Efficient Memory Partitioning for Parallel Data Access via Data Reuse.138-147

Evening Panel  晚上小组

----------------------------------------------------------------------------------------------------------------------

1. Derek Chiou:

Intel Acquires Altera: How Will the World of FPGAs be Affected?148

Technical Session 5:Architecture and Tools  技术会议5：架构和工具

----------------------------------------------------------------------------------------------------------------------

1. Tuan D. A. Nguyen, Akash Kumar:

PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.149-158

1. David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken:

The Stratix™ 10 Highly Pipelined FPGA Architecture.159-168

1. Que Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre:

Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs.169-172

1. Sen Ma, Zeyad Aklah, David Andrews:

Just In Time Assembly of Accelerators.173-178

1. Paul Grigoras, Pavel Burovskiy, Wayne Luk:

CASK: Open-Source Custom Architectures for Sparse Kernels.179-184

Technical Session 6:System-level Tools 技术会议6：系统级工具

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1. Nachiket Kapre, Deheng Ye:

GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths.185-194

1. Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner:

Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis.195-204

1. Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David Lee, Jeffrey Draper:

SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.205-214

Technical Session 7:High-level Synthesis and Tools  技术会议7：高级综合和工具

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1. François Serre, Thomas Holenstein, Markus Püschel:

Optimal Circuits for Streamed Linear Permutations Using RAM.215-223

1. Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:

High Level Synthesis of Complex Applications: An H.264 Video Decoder.224-233

1. Xitong Gao, John Wickerson, George A. Constantinides:

Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis.234-243

Technical Session 8:Applications 技术会议8：应用

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1. David Boland:

Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination.244-253

1. Muhammed Al Kadi, Benedikt Janßen, Michael Hübner:

FGPU: An SIMT-Architecture for FPGAs.254-263

1. Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe:

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.264-273

Poster Session 1  海报会议1

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1. Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda:

A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only).274

1. Ehsan Ghasemi, Paul Chow:

A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only).274

1. Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang:

Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only).274

1. Daolu Zha, Xi Jin, Tian Xiang:

An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only).274

1. Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia:

ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only).275

1. Pingakshya Goswami, Dinesh Bhatia:

Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only).275

1. Matthias Hinkfoth, Ralf Salomon:

Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only).275

1. James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).276

1. Li Ting, Harri Wijaya, Nachiket Kapre:

Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only).276

1. Ronak Kogta, Suresh Purini, Ajit Mathew:

Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only).276

Poster Session 2  海报会议2

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1. Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong:

A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only).277

1. Girish Deshpande, Dinesh K. Bhatia:

An Activity Aware Placement Approach For 3D FPGAs (Abstract Only).277

1. Tianqi Wang, Bo Peng, Xi Jin:

an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only).277

1. Sabrina Zereen, Sundeep Lal, Mohammed A. S. Khalid, Sazzadur Chowdhury:

An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only).278

1. Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang:

An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only).278

1. Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:

Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).278

1. Jing Ye, Yu Hu, Xiaowei Li:

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).279

1. Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni:

Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only).279

1. Yu Bai, Mingjie Lin:

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only).279

1. Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai:

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only).280

Poster Session 3 海报会议3

----------------------------------------------------------------------------------------------------------------------

1. Stefan Visser, Harald Homulle, Edoardo Charbon:

A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only).281

1. Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).281

1. Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou:

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only).281

1. Aaron Landy, Greg Stitt:

Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only).282

1. Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:

Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only).282

1. Yunxuan Yu, Lei He:

FPGA Power Estimation Using Automatic Feature Selection (Abstract Only).282

1. Sizhuo Zhang, Hari Angepat, Derek Chiou:

HGum: Messaging Framework for Hardware Accelerators (Abstact Only).283

1. Sayeh Sharifymoghaddam, Ali Sheikholeslami:

Low-Swing Signaling for FPGA Power Reduction (Abstract Only).283

1. Mohammed Alawad, Mingjie Lin:

Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only).283

1. Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan:

t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only).284

                   

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                                        FPGA2017会议论文

论文下载地址：https://dl.acm.org/citation.cfm?id=3020078&picked=prox

FPGA'17 Workshops   FPGA'17研讨会

----------------------------------------------------------------------------------------------------------------------

1. Hayden Kwok-Hay So, John Wawrzynek:

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs.1

Special Session:The Role of FPGAs in Deep Learning  特别会议：FPGA在深度学习中的作用

----------------------------------------------------------------------------------------------------------------------

1. Andrew Ling, Jason Anderson:

The Role of FPGAs in Deep Learning. 3

1. Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh:

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? 5-14

1. Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang:

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. 15-24

1. Jialiang Zhang, Jing Li:

Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. 25-34

1. Chi Zhang, Viktor K. Prasanna:

Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System. 35-44

1. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. 45-54

Machine Learning   机器学习

----------------------------------------------------------------------------------------------------------------------

1. Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:

An OpenCL™ Deep Learning Accelerator on Arria 10. 55-64

1. Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. 65-74

1. Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William (Bill) J. Dally:

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA. 75-84

Interconnect and Routing 互连和路由

----------------------------------------------------------------------------------------------------------------------

1. Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. 85-94

1. Alex Rodionov, Jonathan Rose:

Synchronization Constraints for Interconnect Synthesis. 95-104

1. Minghua Shen, Guojie Luo:

Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion.105-114

Architecture 架构

----------------------------------------------------------------------------------------------------------------------

1. Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz:

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration.115-124

1. Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer:

Automatic Construction of Program-Optimized FPGA Memory Networks. 125-134

1. Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. 135-140

1. Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre:

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. 141-146

CAD Tools   CAD工具

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1. Gai Liu, Zhiru Zhang:

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping.147-156

1. Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang:

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. 157-166

Panel:FPGAs in the Cloud   专家组：云端的FPGA

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1. George A. Constantinides:

FPGAs in the Cloud. 167

High-Level Synthesis -- Tools and Applications    高级综合--工具和应用

----------------------------------------------------------------------------------------------------------------------

1. Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:

Hardware Synthesis of Weakly Consistent C Concurrency. 169-178

1. Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang:

A New Approach to Automatic Memory Banking using Trace-Based Address Mining. 179-188

1. Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. 189-194

1. Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang:

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. 195-200

1. Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen:

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. 201-206

Graph Processing Applications    图形处理应用

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1. Jialiang Zhang, Soroosh Khoram, Jing Li:

Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search. 207-216

1. Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang:

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. 217-226

1. Xiaoyu Ma, Dan Zhang, Derek Chiou:

FPGA-Accelerated Transactional Execution of Graph Workloads.227-236

Virtualization and Applications   虚拟化和应用

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1. Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:

Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. 237-246

1. Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori:

Energy Efficient Scientific Computing on FPGAs using OpenCL. 247-256

1. Xin Fang, Stratis Ioannidis, Miriam Leeser:

Secure Function Evaluation Using an FPGA Overlay Architecture. 257-266

Applications  应用

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1. Zhuolun He, Guojie Luo:

FPGA Acceleration for Computational Glass-Free Displays. 267-274

1. Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:

Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. 275-284

Poster Session 1 海报会议1

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1. Andy Gean Ye, Karthik Ganesan:

Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only).285

1. Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li:

A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). 285

1. Shuo Wang, Yun Liang:

A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). 285-286

1. Yanqiang Liu, Yao Li, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan:

Scala Based FPGA Design Flow (Abstract Only). 286

1. Girish Deshpande, Dinesh K. Bhatia:

Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only). 286

1. Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao:

A Machine Learning Framework for FPGA Placement (Abstract Only). 286

1. Ralf Salomon, Ralf Joost:

Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only). 287

1. Mostafa Koraei, Magnus Jahre, S. Omid Fatemi:

Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only). 287

1. Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:

Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only). 287

1. Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois:

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).287-288

Poster Session 2  海报会议2

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1. Zhipeng Zhao, James C. Hoe:

Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). 289

1. Christophe Bobda, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat, Laurent Njilla:

Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only). 289

1. Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang:

Accelerating Financial Market Server through Hybrid List Design (Abstract Only). 289-290

1. Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). 290

1. Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). 290

1. Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren:

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only). 290-291

1. Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu:

CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). 291

1. Mohammed Alawad, Mingjie Lin:

Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only).291

1. Stylianos I. Venieris, Christos-Savvas Bouganis:

fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only). 291-292

Poster Session 3  海报会议3

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1. Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari:

FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only).293

1. Yongming Shen, Michael Ferdman, Peter A. Milder:

Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only).293

1. Subho S. Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Daniel Chen, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer:

ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only).293-294

1. Atieh Lotfi, Rajesh K. Gupta:

RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only).294

1. Haoyang Wu, Tao Wang, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu, Songwu Lu:

GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only).294-295

1. Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan:

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only).295

1. Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei:

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only).295

1. Sumanta Chaudhuri:

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only).295-296

1. Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam:

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).296

1. Wei Ting Loke, Chin Yang Koay:

An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only).296

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                                        FPGA2018会议论文

论文下载地址：https://dl.acm.org/citation.cfm?id=3174243&picked=prox

Special Session : Deep Learning  特别会议：深度学习

----------------------------------------------------------------------------------------------------------------------

1. Bita Darvish Rouhani, Mohammad Ghasemzadeh, Farinaz Koushanfar:

CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs.1-10

1. Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang:

C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.11-20

1. Chang Gao, Daniel Neil, Enea Ceolini, Shih-Chii Liu, Tobi Delbrück:

DeltaRNN: A Power-efficient Recurrent Neural Network Accelerator.21-30

1. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato:

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.31-40

Session 1:Architecture 会议1：架构

----------------------------------------------------------------------------------------------------------------------

1. Stephen M. Williams, Mingjie Lin:

Architecture and Circuit Design of an All-Spintronic FPGA.41-50

1. Yue Zha, Jing Li:

Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.51-60

1. Wenyi Feng, Jonathan W. Greene, Alan Mishchenko:

Improving FPGA Performance with a S44 LUT Structure.61-66

Session 2:CAD     会议2：CAD

----------------------------------------------------------------------------------------------------------------------

1. Chin Hau Hoo, Akash Kumar:

ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.67-76

1. Soheil Mohajer, Zhiheng Wang, Kia Bazargan:

Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data.77-86

1. Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter Milder:

A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.87-96

Session 3:Deep Learning    会议3：深度学习

----------------------------------------------------------------------------------------------------------------------

1. Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang:

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA.97-106

1. Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.107-116

1. Hanqing Zeng, Ren Chen, Chi Zhang, Viktor K. Prasanna:

A Framework for Generating High Throughput CNN Implementations on FPGAs.117-126

Session 4:High Level Synthesis 1    会议4：高级综合1

----------------------------------------------------------------------------------------------------------------------

1. Lana Josipovic, Radhika Ghosal, Paolo Ienne:

Dynamically Scheduled High-level Synthesis.127-136

1. Steve Dai, Gai Liu, Zhiru Zhang:

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation.137-146

1. Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.147-152

Session 5:Applications 1   会议5：应用1

----------------------------------------------------------------------------------------------------------------------

1. Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka:

Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL.153-162

1. Jan Dürre, Dario Paradzik, Holger Blume:

A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA.163-172

1. Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis:

Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems.173-182

1. Martin Langhammer, Bogdan Pasca:

High-Performance QR Decomposition for FPGAs.183-188

Session 6:High Level Synthesis 2    会议6：高级综合2

----------------------------------------------------------------------------------------------------------------------

1. Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:

ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development.189-198

1. Juan Escobedo, Mingjie Lin:

Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels.199-208

1. Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:

Architecture Exploration for HLS-Oriented FPGA Debug Overlays.209-218

Session 7:Circuits and Computation Engines    会议7：电路和计算引擎

----------------------------------------------------------------------------------------------------------------------

1. François Serre, Markus Püschel:

Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing Permutations.219-228

1. Jialiang Zhang, Jing Li:

Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform.229-238

1. Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li:

Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.239-248

Session 8:Applications 2    会议8：应用2

----------------------------------------------------------------------------------------------------------------------

1. Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.249-258

1. Shijie Zhou, Rajgopal Kannan, Yu Min, Viktor K. Prasanna:

FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering.259-268

1. Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang:

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.269-278

1. Sean Fox, David Boland, Philip Heng Wai Leong:

FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method.279-284

Poster Session 1 海报会议1

----------------------------------------------------------------------------------------------------------------------

1. Zheming Jin, Kazutomo Yoshii:

Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only).285

1. Ruizhe Zhao, Xinyu Niu, Wayne Luk:

Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only).285

1. Kenichi Koizumi, Kei Hiraki, Mary Inaba:

Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only).285

1. Nachiket Kapre, Tushar Krishna:

FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only).286

1. Yuze Chi, Peipei Zhou, Jason Cong:

An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only).286

1. Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang:

A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).286

1. Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Shumarayev, Aravind Dasu:

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).287

1. Zheming Jin, Hal Finkel:

Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only).287

1. Jason Cong, Zhenman Fang, Yao Hu, Di Wu:

K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only).287

1. Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong:

FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only).288

1. Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang:

Understanding Performance Differences of FPGAs and GPUs: (Abtract Only).288

Poster Session 2 海报会议2

----------------------------------------------------------------------------------------------------------------------

1. Nan Ding, Wei Zhang, Yanhua Ma, Zhenguo Gao:

Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only).289

1. Juexiao Su, Lei He:

Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only).289

1. Chongchong Xu, Chao Wang, Yiwei Zhang, Lei Gong, Xi Li, Xuehai Zhou:

Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only).289

1. Minghua Shen, Wentai Zhang, Nong Xiao, Guojie Luo:

Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only).289

1. Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes:

Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only).290

1. Minghua Shen, Jiaxi Zhang, Nong Xiao, Guojie Luo:

BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only).290

1. Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang:

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only).290

1. Wentai Zhang, Jiaxi Zhang, Minghua Shen, Nong Xiao, Guojie Luo:

Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only).291

1. Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao:

Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only).291

1. Daisuke Suzuki, Takahiro Hanyu:

Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).291

1. Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only).291

Poster Session 3  海报会议3

----------------------------------------------------------------------------------------------------------------------

1. Fady Hussein, Luka Daoud, Nader Rafla:

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only).293

1. Xiaoyu Yu, Dong Ye:

Performance Comparison of Multiples and Target Detection with Imager-driven Processing Mode for Ultrafast-Imager: (Abstract Only).293

1. Shuanglong Liu, Xinyu Niu, Wayne Luk:

A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only.293

1. Mikhail Asiatici, Damian Maiorano, Paolo Ienne:

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only).294

1. Luka Daoud, Muhammad Kamran Latif, Nader Rafla:

SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).294

1. Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun:

FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only).294

1. Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).294

1. Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:

LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).295

1. Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang:

A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only).295

---

                                       FPL2017会议论文

论文下载地址：

https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8049195&punumber=8049195&filter=issueId%20EQ%20%228056751%22&pageNumber=5&pageNumber=1

1. Ivo Bolsens:

"All programmable FPGA, providing hardware efficiency to software programmers".1-3

1. Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka:

01Evaluating high-level design strategies on FPGAs for high-performance computing.1-4

1. Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar:

02Toward a pixel-parallel architecture for graph cuts inference on FPGA.1-4

1. Mohammad Hosseinabady, José Luis Núñez-Yáñez:

03A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.1-4

1. Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan:

04REAPR: Reconfigurable engine for automata processing.1-8

1. Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka:

05Evaluating high-level design strategies on FPGAs for high-performance computing.1-4

1. Ryan A. Cooke, Suhaib A. Fahmy:

06In-network online data analytics with FPGAs.1-2

1. Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens:

07Area-optimized montgomery multiplication on IGLOO 2 FPGAs.1-4

1. Jinnan Ding, Shuguo Li:

08Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition.1-4

1. Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio:

09Optimizing streaming stencil time-step designs via FPGA floorplanning.1-4

1. Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato:

10A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA.1

1. Eric Matthews, Lesley Shannon:

11TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features.1-4

1. Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:

12ARMHEx: A hardware extension for DIFT on ARM-based SoCs.1-7

1. Michal Kekely, Jan Korenek:

13Mapping of P4 match action tables to FPGA.1-2

1. Jinnan Ding, Shuguo Li:

14Broken-Karatsuba multiplication and its application to Montgomery modular multiplication.1-4

1. Hongyuan Ding, Miaoqing Huang:

15PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system.1-8

1. Hiroki Nakahara, Tomoya Fujii, Shimpei Sato:

16A fully connected layer elimination for a binarizec convolutional neural network on an FPGA.1-4

1. Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer:

17Complete activation scheme for FPGA-oriented IP cores design protection.1

1. Size Xiao, Neil Bergmann, Adam Postula:

18Parallel RRT∗ architecture design for motion planning.1-4

1. Ioannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas:

19A programming model and runtime system for approximation-aware heterogeneous computing.1-4

1. Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang:

20PAAS: A system level simulator for heterogeneous computing architectures.1-8

1. Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi:

21A partial reconfiguration based microphone array network emulator.1-4

1. Kizhepatt Vipin, Jan Gray, Nachiket Kapre:

22Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs.1-8

1. Mitra Purandare, Raphael Polig, Christoph Hagleitner:

23Accelerated analysis of Boolean gene regulatory networks.1-6

1. Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk:

24F-C3D: FPGA-based 3-dimensional convolutional neural network.1-4

1. Vladimir Rozic, Bohan Yang, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede:

25The Monte Carlo PUF.1-6

1. Gaël Deest, Tomofumi Yuki, Sanjay Rajopadhye, Steven Derrien:

26One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs.1-8

1. Mirjana Stojilovic:

27Parallel FPGA routing: Survey and challenges.1-8

1. Yehya Nasser, Jean-Christophe Prévotet, M. Heiard, Jordane Lorandel:

28Dynamic power estimation based on switching activity propagation.1-2

1. Muhsen Owaida, Hantian Zhang, Ce Zhang, Gustavo Alonso:

29Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms.1-8

1. Kevin Nam, Blair Fort, Stephen Dean Brown:

30FISH: Linux system calls for FPGA accelerators.1-4

1. Benedikt Janßen, Pascal Zimprich, Michael Hübner:

31A dynamic partial reconfigurable overlay concept for PYNQ.1-4

1. Yanzhe Li, Kai Huang, Luc Claesen:

32High-quality view interpolation based on depth maps and its hardware implementation.1-6

1. Stelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas:

33VineTalk: Simplifying software access and sharing of FPGAs in datacenters.1-4

1. Shengjia Shao, Wayne Luk:

34Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation.1-6

1. Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow:

35Heterogeneous virtualized network function framework for the data center.1-8

1. Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen:

36OpenSoC system architect: An open toolkit for building soft-cores on FPGAs.1

1. Yohann Uguen, Florent de Dinechin, Steven Derrien:

37Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations.1-8

1. James Stanley Targett, Peter D. Düben, Wayne Luk:

38Validating optimisations for chaotic simulations.1-4

1. Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho:

39A high-throughput reconfigurable processing array for neural networks.1-4

1. Alexander Wild, Georg T. Becker, Tim Güneysu:

40A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs.1-7

1. Christos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos:

41A generic high throughput architecture for stream processing.1-5

1. Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard:

42Transparent memory encryption and authentication.1-6

1. Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:

43Reliable SEU monitoring and recovery using a programmable configuration controller.1-6

1. Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:

44ARMHEx: A framework for efficient DIFT in real-world SoCs.1

1. Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton:

45Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.1-4

1. Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch:

46Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.1-8

1. Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:

47In-switch approximate processing: Delayed tasks management for MapReduce applications.1-4

1. Lijuan Li, Shuguo Li:

48High throughput AES encryption/decryption with efficient reordering and merging techniques.1-4

1. Nachiket Kapre:

49Deflection-routed butterfly fat trees on FPGAs.1-8

1. Stephan Nolting, Lin Liu, Guillermo Payá Vayá:

50Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices.1-4

1. Jose Raul Garcia Ordaz, Dirk Koch:

51Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit.1-4

1. Sadegh Yazdanshenas, Vaughn Betz:

52Quantifying and mitigating the costs of FPGA virtualization.1-7

1. William Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj:

53Comparison of hardware and software implementations of selected lightweight block ciphers.1-4

1. Thomas Townsend, Brent E. Nelson:

54Vivado design interface: An export/import capability for Vivado FPGA designs.1-7

1. Junyi Liu, John Wickerson, George A. Constantinides:

55Tile size selection for optimized memory reuse in high-level synthesis.1-8

1. Umar Afzaal, Jeong-A Lee:

56FPGA-based design of a self-checking TMR voter.1-4

1. Nikolaos Alachiotis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos:

57Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study.1-4

1. Ryouhei Maeda, Tsutomu Maruyama:

58An implementation method of poisson image editing on FPGA.1-6

1. Dimitrios Bozikas, Nikolaos Alachiotis, Pavlos Pavlidis, Euripides Sotiriades, Apostolos Dollas:

59Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibrium.1-8

1. Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris:

60FPGA acceleration of spark applications in a Pynq cluster.1

1. Yifeng Mo, Shuguo Li:

61Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs.1-6

1. Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch:

62A security library for FPGA interlays.1-4

1. Adewale Adetomi, Godwin Enemali, Tughrul Arslan:

63Relocation-aware communication network for circuits on Xilinx FPGAs.1-7

1. Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz:

64Find the real speed limit: FPGA CAD for chip-specific application delay measurement.1-8

1. Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang:

65Accelerating low bit-width convolutional neural networks with embedded FPGA.1-4

1. Shuangnan Liu, Benjamin Carrión Schäfer:

66Learning-based interconnect-aware dataflow accelerator optimization.1-7

1. Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser:

67FPGA modeling techniques for detecting and demodulating multiple wireless protocols.1-4

1. Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:

68High performance binary neural networks on the Xeon+FPGA™ platform.1-4

1. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:

69An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.1-8

1. R. Aggleton, L. Ardila-Perez, F. A. Ball, Matthias Norbert Balzer, J. Brooke, L. Calligaris, M. Caselle, D. Cieri, E. J. Clement, G. Hall, K. Harder, P. R. Hobson, G. M. Iles, T. James, K. Manolopoulos, T. Matsushita, A. D. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. D. Reid, A. W. Rose, Oliver Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. P. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber:

70A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN.1-4

1. Grace Zgheib, Paolo Ienne:

71Evaluating FPGA clusters under wide ranges of design parameters.1-8

1. Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello:

72Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.1-4

1. Stylianos I. Venieris, Christos-Savvas Bouganis:

73Latency-driven design for FPGA-based convolutional neural networks.1-8

1. Simon Joel Schmidt, David Boland:

74Dynamic bitwidth assignment for efficient dot products.1-8

1. David J. Greaves:

75Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo.1

1. Konstantinos Boikos, Christos-Savvas Bouganis:

76A high-performance system-on-chip architecture for direct tracking for SLAM.1-7

1. Zhe Lin, Wei Zhang, Sharad Sinha:

77Decision tree based hardware power monitoring for run time dynamic power management in FPGA.1-8

1. Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen:

78High-performance video content recognition with long-term recurrent convolutional network for FPGA.1-4

1. Thomas B. Preußer:

79Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs.1-7

1. Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely:

80Line rate programmable packet processing in 100Gb networks.1

1. Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá:

81Application-specific soft-core vector processor for advanced driver assistance systems.1-2

1. Subho S. Banerjee, Mohamed El-Hadedy, Ching Y. Tan, Zbigniew T. Kalbarczyk, Steven S. Lumetta, Ravishankar K. Iyer:

82On accelerating pair-HMM computations in programmable hardware.1-8

1. Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:

83Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts.1-8

1. Henry Block, Tsutomu Maruyama:

84An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization.1-8

1. Dennis R. E. Gnad, Fabian Oboril, Mehdi Baradaran Tahoori:

85Voltage drop-based fault attacks on FPGAs using valid bitstreams.1-7

1. Yu Ting Chen, Jason Helge Anderson:

86Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software.1-8

1. James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:

87STRIPE: Signal selection for runtime power estimation.1-8

1. ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li:

88An implementation of list successive cancellation decoder with large list size for polar codes.1-4

1. Tobias Kenter, Jens Förstner, Christian Plessl:

89Flexible FPGA design for FDTD using OpenCL.1-7

1. Brad L. Hutchings, Michael J. Wirthlin:

90Rapid implementation of a partially reconfigurable video system with PYNQ.1-8

1. Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano:

91Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.1-4

1. Lester Kalms, Diana Göhringer:

92Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs.1-4

1. Festus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda:

93Shielding non-trusted IPs in SoCs.1-4

1. Julian Caba, Fernando Rincón, Julio Dondo Gazzano:

94Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks.1-2

1. Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy:

95Scalable high-performance architecture for convolutional ternary neural networks on FPGA.1-7

1. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:

96Body bias optimization for variable pipelined CGRA.1-4

1. Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li:

97Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.1-4

1. Jiayi Sheng, Chen Yang, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt:

98HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics.1-4

1. João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:

99K-means clustering on CGRA.1-4

1. Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:

100FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.1

1. Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond:

101FPGA acceleration of multilevel ORB feature extraction for computer vision.1-8

1. Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi:

102Demonstration of a partial reconfiguration based microphone array network emulator.1

1. Oron Port, Yoav Etsion:

103DFiant: A dataflow hardware description language.1-4

1. Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy:

104Phase calibrated ring oscillator PUF design and implementation on FPGAs.1-8

1. John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, Timothy Sherwood:

105A pythonic approach for rapid hardware prototyping and instrumentation.1-7

1. Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang:

106FPGA acceleration of the scoring process of X!TANDEM for protein identification.1-4

1. Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang:

107Exploring the potential of reconfigurable platforms for order book update.1-8

1. Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:

108Parallel dot-products for deep learning on FPGA.1-4

1. David Sidler, Muhsen Owaida, Zsolt István, Kaan Kara, Gustavo Alonso:

109doppioDB: A hardware accelerated database.1

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