Verilog乘法

reg [15:0] m1;
reg [15:0] m2;
reg [31:0] d;
无符号乘法：
d <= {16’d0,m1}*{16’d0,m2};
有符号乘法：
d<={16{m1[15]},m1}*{16{m1[15]},m2};  //即符号位扩展

module mul(
    iCLK,
    iRST_N,
    oD
);

input iCLK;
input iRST_N;
output reg [31:0] oD;

reg [15:0] m1;
reg [15:0] m2;
reg div;
always@(posedge iCLK or negedge iRST_N)begin
    if(!iRST_N)begin
        div<=1'b0;
    end
    else begin
        div <= ~div;
    end
end
always@(posedge iCLK or negedge iRST_N)begin
    if(!iRST_N)begin
        m1<=16'd0;
    end
    else if(div) begin
        m1<=m1+16'd1;
    end
end
always@(posedge iCLK or negedge iRST_N)begin
    if(!iRST_N)begin
        m2<=16'd0;
    end
    else if( div && m1 == 16'hFFFF)begin
        m2 <= m2 + 16'd1;
    end
end
always@(posedge iCLK or negedge iRST_N)begin
    if(!iRST_N)begin
        oD <= 32'd0;
    end
    else begin
        oD <= {16'd0,m1}*{16'd0,m2};
    end
end
endmodule

#include
#include
int main()
{
    printf("%X/n",-1*7);
    printf("%X/n",0xFFFFFFFF*7);
    printf("%d/n",-1*7);
    printf("%d/n",0xFFFFFFFF*7);
    printf("Hello world!/n");
    return 0;
}