zynq_devicetree

device tree最开始的是skeleton.dtsi

  http://blog.csdn.net/shichaog/article/details/51249106
 /*
  * Skeleton device tree; the bare minimum needed to boot; just include and
  * add a compatible value.  The bootloader will typically populate the memory
  * node.
  */

 / {
     #address-cells = <1>;
     #size-cells = <1>;
     chosen { };
     aliases { };
     memory { device_type = "memory"; reg = <0 0>; };
 };

这是32位体系架构的设备树的skeleton，address-cells那行表示的是用32bit表示地址，寄存器也是用32bit来表示。接下来设备树里的东西是和zynq-7000这款芯片cpu息息相关的定义。将cpu以及外设都定义在此处。

 《zynq-7000.dtsi》
   1 /*
   2  *  Copyright (C) 2011 - 2014 Xilinx
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16     compatible = "xlnx,zynq-7000";
  17
  18     cpus {
  19         #address-cells = <1>;
  20         #size-cells = <0>;
  21
  22         cpu@0 {
  23             compatible = "arm,cortex-a9";
  24             device_type = "cpu";
  25             reg = <0>;
  26             clocks = <&clkc 3>;
  27             clock-latency = <1000>;
  28             cpu0-supply = <®ulator_vccpint>;
  29             operating-points = <
  30                 /* kHz    uV */
  31                 666667  1000000
  32                 333334  1000000
  33             >;
  34         };
  35
  36         cpu@1 {
  37             compatible = "arm,cortex-a9";
  38             device_type = "cpu";
  39             reg = <1>;
  40             clocks = <&clkc 3>;
  41         };
  42     };
  43
  44     pmu {
  45         compatible = "arm,cortex-a9-pmu";
  46         interrupts = <0 5 4>, <0 6 4>;
  47         interrupt-parent = <&intc>;
  48         reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  49     };
  50
  51     regulator_vccpint: fixedregulator@0 {
  52         compatible = "regulator-fixed";
  53         regulator-name = "VCCPINT";
  54         regulator-min-microvolt = <1000000>;
  55         regulator-max-microvolt = <1000000>;
  56         regulator-boot-on;
  57         regulator-always-on;
  58     };
  59
  60     amba: amba {
  61         compatible = "simple-bus";
  62         #address-cells = <1>;
  63         #size-cells = <1>;
  64         interrupt-parent = <&intc>;
  65         ranges;
  66
  67         adc: adc@f8007100 {
  68             compatible = "xlnx,zynq-xadc-1.00.a";
  69             reg = <0xf8007100 0x20>;
  70             interrupts = <0 7 4>;
  71             interrupt-parent = <&intc>;
  72             clocks = <&clkc 12>;
  73         };
  74
  75         can0: can@e0008000 {
  76             compatible = "xlnx,zynq-can-1.0";
  77             status = "disabled";
  78             clocks = <&clkc 19>, <&clkc 36>;
  79             clock-names = "can_clk", "pclk";
  80             reg = <0xe0008000 0x1000>;
  81             interrupts = <0 28 4>;
  82             interrupt-parent = <&intc>;
  83             tx-fifo-depth = <0x40>;
  84             rx-fifo-depth = <0x40>;
  85         };
  86
  87         can1: can@e0009000 {
  88             compatible = "xlnx,zynq-can-1.0";
  89             status = "disabled";
  90             clocks = <&clkc 20>, <&clkc 37>;
  91             clock-names = "can_clk", "pclk";
  92             reg = <0xe0009000 0x1000>;
  93             interrupts = <0 51 4>;
  94             interrupt-parent = <&intc>;
  95             tx-fifo-depth = <0x40>;
  96             rx-fifo-depth = <0x40>;
  97         };
  98
  99         gpio0: gpio@e000a000 {
 100             compatible = "xlnx,zynq-gpio-1.0";
 101             #gpio-cells = <2>;
 102             #interrupt-cells = <2>;
 103             clocks = <&clkc 42>;
 104             gpio-controller;
 105             interrupt-controller;
 106             interrupt-parent = <&intc>;
 107             interrupts = <0 20 4>;
 108             reg = <0xe000a000 0x1000>;
 109         };
 110
 111         i2c0: i2c@e0004000 {
 112             compatible = "cdns,i2c-r1p10";
 113             status = "disabled";
 114             clocks = <&clkc 38>;
 115             interrupt-parent = <&intc>;
 116             interrupts = <0 25 4>;
 117             reg = <0xe0004000 0x1000>;
 118             #address-cells = <1>;
 119             #size-cells = <0>;
 120         };
 121
 122         i2c1: i2c@e0005000 {
 123             compatible = "cdns,i2c-r1p10";
 124             status = "disabled";
 125             clocks = <&clkc 39>;
 126             interrupt-parent = <&intc>;
 127             interrupts = <0 48 4>;
 128             reg = <0xe0005000 0x1000>;
 129             #address-cells = <1>;
 130             #size-cells = <0>;
 131         };
 132
 133         intc: interrupt-controller@f8f01000 {
 134             compatible = "arm,cortex-a9-gic";
 135             #interrupt-cells = <3>;
 136             interrupt-controller;
 137             reg = <0xF8F01000 0x1000>,
 138                   <0xF8F00100 0x100>;
 139         };
 140
 141         L2: cache-controller@f8f02000 {
 142             compatible = "arm,pl310-cache";
 143             reg = <0xF8F02000 0x1000>;
 144             interrupts = <0 2 4>;
 145             arm,data-latency = <3 2 2>;
 146             arm,tag-latency = <2 2 2>;
 147             cache-unified;
 148             cache-level = <2>;
 149         };
 150
 151         mc: memory-controller@f8006000 {
 152             compatible = "xlnx,zynq-ddrc-a05";
 153             reg = <0xf8006000 0x1000>;
 154         };
 155
 156         ocmc: ocmc@f800c000 {
 157             compatible = "xlnx,zynq-ocmc-1.0";
 158             interrupt-parent = <&intc>;
 159             interrupts = <0 3 4>;
 160             reg = <0xf800c000 0x1000>;
 161         };
 162
 163         uart0: serial@e0000000 {
 164             compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 165             status = "disabled";
 166             clocks = <&clkc 23>, <&clkc 40>;
 167             clock-names = "uart_clk", "pclk";
 168             reg = <0xE0000000 0x1000>;
 169             interrupts = <0 27 4>;
 170         };
 171
 172         uart1: serial@e0001000 {
 173             compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 174             status = "disabled";
 175             clocks = <&clkc 24>, <&clkc 41>;
 176             clock-names = "uart_clk", "pclk";
 177             reg = <0xE0001000 0x1000>;
 178             interrupts = <0 50 4>;
 179         };
 180
 181         spi0: spi@e0006000 {
 182             compatible = "xlnx,zynq-spi-r1p6";
 183             reg = <0xe0006000 0x1000>;
 184             status = "disabled";
 185             interrupt-parent = <&intc>;
 186             interrupts = <0 26 4>;
 187             clocks = <&clkc 25>, <&clkc 34>;
 188             clock-names = "ref_clk", "pclk";
 189             #address-cells = <1>;
 190             #size-cells = <0>;
 191         };
 192
 193         spi1: spi@e0007000 {
 194             compatible = "xlnx,zynq-spi-r1p6";
 195             reg = <0xe0007000 0x1000>;
 196             status = "disabled";
 197             interrupt-parent = <&intc>;
 198             interrupts = <0 49 4>;
 199             clocks = <&clkc 26>, <&clkc 35>;
 200             clock-names = "ref_clk", "pclk";
 201             #address-cells = <1>;
 202             #size-cells = <0>;
 203         };
 204
 205         qspi: spi@e000d000 {
 206             clock-names = "ref_clk", "pclk";
 207             clocks = <&clkc 10>, <&clkc 43>;
 208             compatible = "xlnx,zynq-qspi-1.0";
 209             status = "disabled";
 210             interrupt-parent = <&intc>;
 211             interrupts = <0 19 4>;
 212             reg = <0xe000d000 0x1000>;
 213             #address-cells = <1>;
 214             #size-cells = <0>;
 215         };
 216
 217         smcc: memory-controller@e000e000 {
 218             #address-cells = <1>;
 219             #size-cells = <1>;
 220             status = "disabled";
 221             clock-names = "memclk", "aclk";
 222             clocks = <&clkc 11>, <&clkc 44>;
 223             compatible = "arm,pl353-smc-r2p1";
 224             interrupt-parent = <&intc>;
 225             interrupts = <0 18 4>;
 226             ranges ;
 227             reg = <0xe000e000 0x1000>;
 228             nand0: flash@e1000000 {
 229                 status = "disabled";
 230                 compatible = "arm,pl353-nand-r2p1";
 231                 reg = <0xe1000000 0x1000000>;
 232                 #address-cells = <0x1>;
 233                 #size-cells = <0x1>;
 234             };
 235             nor0: flash@e2000000 {
 236                 status = "disabled";
 237                 compatible = "cfi-flash";
 238                 reg = <0xe2000000 0x2000000>;
 239                 #address-cells = <1>;
 240                 #size-cells = <1>;
 241             };
 242         };
 243
 244         gem0: ethernet@e000b000 {
 245             compatible = "cdns,zynq-gem", "cdns,gem";
 246             reg = <0xe000b000 0x1000>;
 247             status = "disabled";
 248             interrupts = <0 22 4>;
 249             clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 250             clock-names = "pclk", "hclk", "tx_clk";
 251             #address-cells = <1>;
 252             #size-cells = <0>;
 253         };
 254
 255         gem1: ethernet@e000c000 {
 256             compatible = "cdns,zynq-gem", "cdns,gem";
 257             reg = <0xe000c000 0x1000>;
 258             status = "disabled";
 259             interrupts = <0 45 4>;
 260             clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 261             clock-names = "pclk", "hclk", "tx_clk";
 262             #address-cells = <1>;
 263             #size-cells = <0>;
 264         };
 265
 266         sdhci0: sdhci@e0100000 {
 267             compatible = "arasan,sdhci-8.9a";
 268             status = "disabled";
 269             clock-names = "clk_xin", "clk_ahb";
 270             clocks = <&clkc 21>, <&clkc 32>;
 271             interrupt-parent = <&intc>;
 272             interrupts = <0 24 4>;
 273             reg = <0xe0100000 0x1000>;
 274         };
 275
 276         sdhci1: sdhci@e0101000 {
 277             compatible = "arasan,sdhci-8.9a";
 278             status = "disabled";
 279             clock-names = "clk_xin", "clk_ahb";
 280             clocks = <&clkc 22>, <&clkc 33>;
 281             interrupt-parent = <&intc>;
 282             interrupts = <0 47 4>;
 283             reg = <0xe0101000 0x1000>;
 284         };
 285
 286         slcr: slcr@f8000000 {
 287             #address-cells = <1>;
 288             #size-cells = <1>;
 289             compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
 290             reg = <0xF8000000 0x1000>;
 291             ranges;
 292             clkc: clkc@100 {
 293                 #clock-cells = <1>;
 294                 compatible = "xlnx,ps7-clkc";
 295                 fclk-enable = <0xf>;
 296                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 297                         "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 298                         "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 299                         "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 300                         "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 301                         "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 302                         "gem1_aper", "sdio0_aper", "sdio1_aper",
 303                         "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 304                         "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 305                         "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 306                         "dbg_trc", "dbg_apb";
 307                 reg = <0x100 0x100>;
 308             };
 309
 310             rstc: rstc@200 {
 311                 compatible = "xlnx,zynq-reset";
 312                 reg = <0x200 0x48>;
 313                 #reset-cells = <1>;
 314                 syscon = <&slcr>;
 315             };
 316
 317             pinctrl0: pinctrl@700 {
 318                 compatible = "xlnx,pinctrl-zynq";
 319                 reg = <0x700 0x200>;
 320                 syscon = <&slcr>;
 321             };
 322         };
 323
 324         dmac_s: dmac@f8003000 {
 325             compatible = "arm,pl330", "arm,primecell";
 326             reg = <0xf8003000 0x1000>;
 327             interrupt-parent = <&intc>;
 328             interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 329                 "dma4", "dma5", "dma6", "dma7";
 330             interrupts = <0 13 4>,
 331                          <0 14 4>, <0 15 4>,
 332                          <0 16 4>, <0 17 4>,
 333                          <0 40 4>, <0 41 4>,
 334                          <0 42 4>, <0 43 4>;
 335             #dma-cells = <1>;
 336             #dma-channels = <8>;
 337             #dma-requests = <4>;
 338             clocks = <&clkc 27>;
 339             clock-names = "apb_pclk";
 340         };
 341
 342         devcfg: devcfg@f8007000 {
 343             compatible = "xlnx,zynq-devcfg-1.0";
 344             interrupt-parent = <&intc>;
 345             interrupts = <0 8 4>;
 346             reg = <0xf8007000 0x100>;
 347             clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
 348             clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
 349             syscon = <&slcr>;
 350         };
 351
 352         global_timer: timer@f8f00200 {
 353             compatible = "arm,cortex-a9-global-timer";
 354             reg = <0xf8f00200 0x20>;
 355             interrupts = <1 11 0x301>;
 356             interrupt-parent = <&intc>;
 357             clocks = <&clkc 4>;
 358         };
 359
 360         ttc0: timer@f8001000 {
 361             interrupt-parent = <&intc>;
 362             interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 363             compatible = "cdns,ttc";
 364             clocks = <&clkc 6>;
 365             reg = <0xF8001000 0x1000>;
 366         };
 367
 368         ttc1: timer@f8002000 {
 369             interrupt-parent = <&intc>;
 370             interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 371             compatible = "cdns,ttc";
 372             clocks = <&clkc 6>;
 373             reg = <0xF8002000 0x1000>;
 374         };
 375
 376         scutimer: timer@f8f00600 {
 377             interrupt-parent = <&intc>;
 378             interrupts = <1 13 0x301>;
 379             compatible = "arm,cortex-a9-twd-timer";
 380             reg = <0xf8f00600 0x20>;
 381             clocks = <&clkc 4>;
 382         };
 383
 384         usb0: usb@e0002000 {
 385             compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 386             status = "disabled";
 387             clocks = <&clkc 28>;
 388             interrupt-parent = <&intc>;
 389             interrupts = <0 21 4>;
 390             reg = <0xe0002000 0x1000>;
 391             phy_type = "ulpi";
 392         };
 393
 394         usb1: usb@e0003000 {
 395             compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 396             status = "disabled";
 397             clocks = <&clkc 29>;
 398             interrupt-parent = <&intc>;
 399             interrupts = <0 44 4>;
 400             reg = <0xe0003000 0x1000>;
 401             phy_type = "ulpi";
 402         };
 403
 404         watchdog0: watchdog@f8005000 {
 405             clocks = <&clkc 45>;
 406             compatible = "cdns,wdt-r1p2";
 407             interrupt-parent = <&intc>;
 408             interrupts = <0 9 1>;
 409             reg = <0xf8005000 0x1000>;
 410             timeout-sec = <10>;
 411         };
 412     };
 413 };

接下来是对上面定义的节点一些属性的补充。

 《zynq.dtsi》
  1
   2 /include/ "zynq-7000.dtsi"
   3
   4 /*
   5  * The Xilinx EMACPS and the Cadance GEM drivers are for the same IP core, but
   6  * the drivers are not fully feature compatible. We stay with the Xilinx driver
   7  * for now. The main issue is the lack of support for gmii2rgmii when using the
   8  * Cadance driver.
   9  */
  10 &amba {
  11     eth: eth@e000b000 {
  12         compatible = "xlnx,ps7-ethernet-1.00.a";
  13         reg = <0xe000b000 0x1000>;
  14         interrupts = <0 22 4>;
  15         interrupt-parent = <&intc>;
  16         #address-cells = <0x1>;
  17         #size-cells = <0x0>;
  18
  19         clock-names = "ref_clk", "aper_clk";
  20         clocks = <&clkc 13>, <&clkc 30>;
  21
  22         xlnx,enet-clk-freq-hz = <0x17d7840>;
  23         xlnx,enet-reset = "MIO 11";
  24         xlnx,enet-slcr-1000mbps-div0 = <0x8>;
  25         xlnx,enet-slcr-1000mbps-div1 = <0x1>;
  26         xlnx,enet-slcr-100mbps-div0 = <0x8>;
  27         xlnx,enet-slcr-100mbps-div1 = <0x5>;
  28         xlnx,enet-slcr-10mbps-div0 = <0x8>;
  29         xlnx,enet-slcr-10mbps-div1 = <0x32>;
  30         xlnx,eth-mode = <0x1>;
  31         xlnx,has-mdio = <0x1>;
  32         xlnx,ptp-enet-clock = <111111115>;
  33     };
  34
  35 };
  36
  37 /delete-node/ &gem0;
  38 /delete-node/ &gem1;
  39
  40 / {
  41     interrupt-parent = <&intc>;
  42
  43     aliases: aliases {
  44         ethernet0 = ð
  45         serial0 = &uart1;
  46     };
  47 };
  48
  49 &usb0 {
  50     status = "okay";
  51     dr_mode = "host"; /* This breaks OTG mode */
  52 };
  53
  54 &uart1 {
  55     status = "okay";
  56 };
  57
  58 &sdhci0 {
  59     status = "okay";
  60 };

接下来是板级节点属性的定义, memory的reg属性表示内存的起始地址是0，大小是0x2000_0000(512M)，这正是板子内存大小。

 《zynq-zed.dtsi》
  1 /include/ "zynq.dtsi"
   2
   3 / {
   4     model = "Xilinx Zynq ZED";
   5     memory {
   6         device_type = "memory";
   7         reg = <0x000000000 0x20000000>;
   8     };
   9
  10     chosen {
  11 //      bootargs = "console=ttyPS0,115200 root=/dev/ram rw initrd=0x1100000,33M ip=:::::eth0:dhcp earlyprintk";
  12         bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
  13         linux,stdout-path = "/amba@0/uart@E0001000";
  14     };
  15 };
  16
  17 ð {
  18     phy-handle = <&phy0>;
  19     phy-mode = "rgmii-id";
  20
  21     phy0: phy@0 {
  22         compatible = "marvell,88e1510";
  23         device_type = "ethernet-phy";
  24         reg = <0x0>;
  25         marvell,reg-init=<3 16 0xff00 0x1e 3 17 0xfff0 0x0a>;
  26     };
  27 };
  28
  29 &usb0 {
  30     xlnx,phy-reset-gpio = <&gpio0 85 0>;
  31 };
  32
  33 &qspi {
  34     status = "okay";
  35     is-dual = <0>;
  36     num-cs = <1>;
  37     primary_flash: ps7-qspi@0 {
  38         #address-cells = <1>;
  39         #size-cells = <1>;
  40         compatible = "n25q128a11";
  41         reg = <0x0>;
  42         spi-max-frequency = <50000000>;
  43         partition@0x00000000 {
  44             label = "boot";
  45             reg = <0x00000000 0x00500000>;
  46         };
  47         partition@0x00500000 {
  48             label = "bootenv";
  49             reg = <0x00500000 0x00020000>;
  50         };
  51         partition@0x00520000 {
  52             label = "config";
  53             reg = <0x00520000 0x00020000>;
  54         };
  55         partition@0x00540000 {
  56             label = "image";
  57             reg = <0x00540000 0x00a80000>;
  58         };
  59         partition@0x00fc0000 {
  60             label = "spare";
  61             reg = <0x00fc0000 0x00000000>;
  62         };
  63     };
  64 };

在下来，就是这里使用了hdmi视频和zed board上的音频以及其它外设资源定义了，这些外设使用了PL（program logic资源，即FPGA资源）。

 《zynq-zed-adv7511.dtsi》
  1 / {
   2     fpga_axi: fpga-axi@0 {
   3         compatible = "simple-bus";
   4         #address-cells = <0x1>;
   5         #size-cells = <0x1>;
   6         ranges;
   7
   8         i2c@41600000 {
   9             compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
  10             interrupt-parent = <&intc>;
  11             interrupts = <0 58 0x4>;
  12             reg = <0x41600000 0x10000>;
  13
  14             #size-cells = <0>;
  15             #address-cells = <1>;
  16
  17             adv7511: adv7511@39 {
  18                 compatible = "adi,adv7511";
  19                 reg = <0x39>;
  20
  21                 adi,input-style = <0x02>;
  22                 adi,input-id = <0x01>;
  23                 adi,input-color-depth = <0x3>;
  24                 adi,sync-pulse = <0x03>;
  25                 adi,bit-justification = <0x01>;
  26                 adi,up-conversion = <0x00>;
  27                 adi,timing-generation-sequence = <0x00>;
  28                 adi,vsync-polarity = <0x02>;
  29                 adi,hsync-polarity = <0x02>;
  30                 adi,tdms-clock-inversion;
  31                 adi,clock-delay = <0x03>;
  32
  33                 ports {
  34                     #address-cells = <1>;
  35                     #size-cells = <0>;
  36
  37                     port@0 {
  38                         reg = <0>;
  39                         adv7511_in: endpoint {
  40                             remote-endpoint = <&axi_hdmi_out>;
  41                         };
  42                     };
  43
  44                     port@1 {
  45                         reg = <1>;
  46                     };
  47                 };
  48             };
  49
  50             adau1761: adau1761@3b {
  51                 compatible = "adi,adau1761";
  52                 reg = <0x3b>;
  53             };
  54         };
  55
  56         axi_vdma_0: axivdma@43000000 {
  57             compatible = "xlnx,axi-vdma-1.00.a";
  58             #address-cells = <1>;
  59             #size-cells = <1>;
  60             #dma-cells = <1>;
  61             #dma-channels = <1>;
  62             reg = <0x43000000 0x1000>;
  63             xlnx,num-fstores = <0x3>;
  64             dma-channel@43000000 {
  65                 compatible = "xlnx,axi-vdma-mm2s-channel";
  66                 interrupts = <0 59 0x4>;
  67                 xlnx,datawidth = <0x40>;
  68                 xlnx,genlock-mode = <0x0>;
  69                 xlnx,include-dre = <0x0>;
  70             };
  71         };
  72
  73         hdmi_clock: axi-clkgen@79000000 {
  74             compatible = "adi,axi-clkgen-2.00.a";
  75             reg = <0x79000000 0x10000>;
  76             #clock-cells = <0>;
  77             clocks = <&clkc 16>;
  78         };
  79
  80         axi_hdmi@70e00000 {
  81             compatible = "adi,axi-hdmi-tx-1.00.a";
  82             reg = <0x70e00000 0x10000>;
  83             dmas = <&axi_vdma_0 0>;
  84             dma-names = "video";
  85             clocks = <&hdmi_clock>;
  86
  87             port {
  88                 axi_hdmi_out: endpoint {
  89                     remote-endpoint = <&adv7511_in>;
  90                 };
  91             };
  92         };
  93
  94         audio_clock: audio_clock {
  95             compatible = "fixed-clock";
  96             #clock-cells = <0>;
  97             clock-frequency = <12288000>;
  98         };
  99
 100         axi_spdif_tx_0: axi-spdif-tx@0x75c00000 {
 101             compatible = "adi,axi-spdif-tx-1.00.a";
 102             reg = <0x75c00000 0x1000>;
 103             dmas = <&dmac_s 0>;
 104             dma-names = "tx";
 105             clocks = <&clkc 15>, <&audio_clock>;
 106             clock-names = "axi", "ref";
 107         };
 108
 109         adv7511_hdmi_snd: adv7511_hdmi_snd {
 110             compatible = "adv7511-hdmi-snd";
 111             audio-codec = <&adv7511>;
 112             cpu-dai = <&axi_spdif_tx_0>;
 113         };
 114
 115         axi_i2s_0: axi-i2s@0x77600000 {
 116             compatible = "adi,axi-i2s-1.00.a";
 117             reg = <0x77600000 0x1000>;
 118             dmas = <&dmac_s 1 &dmac_s 2>;
 119             dma-names = "tx", "rx";
 120             clocks = <&clkc 15>, <&audio_clock>;
 121             clock-names = "axi", "ref";
 122         };
 /* 第116行的字段和的260行相互匹配，reg这个字段在vivado的block design中Address Editor可以看出0x77600000是i2s是基地址，
 0x1000是寄存器段的大小，dmas是dma字段，使用了PS端的dmac 1和dmac 2，dmac 0在vivado的设计中并没有设备，所以spdif的驱动并没有注册，这两个dma分别用于发送和
 接收，clocks字段第一个是axi接口的时钟，第二个是iis的master时钟，这里就是12.288MHz。 这个IIS 控制器dai，实际上在PL里，但是相对adau1761这些外置dai而言，它们是cpu dai*/
 123
 124         zed_sound: zed_sound {
 125             compatible = "digilent,zed-sound";
 126             audio-codec = <&adau1761>;
 127             cpu-dai = <&axi_i2s_0>;
 128         };
 /*这个字段的125行是和 的144相呼应的，设备树表示，adau1761将和axi_i2s_0进行音频数据交互，该文件描述了codec侧的dai*/


  129     };
 130
 131     leds {
 132         compatible = "gpio-leds";
 133         ld0 {
 134             label = "ld0:red";
 135             gpios = <&gpio0 73 0>;
 136         };
 137
 138         ld1 {
 139             label = "ld1:red";
 140             gpios = <&gpio0 74 0>;
 141         };
 142
 143         ld2 {
 144             label = "ld2:red";
 145             gpios = <&gpio0 75 0>;
 146         };
 147
 148         ld3 {
 149             label = "ld3:red";
 150             gpios = <&gpio0 76 0>;
 151         };
 152
 153         ld4 {
 154             label = "ld4:red";
 155             gpios = <&gpio0 77 0>;
 156         };
 157
 158         ld5 {
 159             label = "ld5:red";
 160             gpios = <&gpio0 78 0>;
 161         };
 162
 163         ld6 {
 164             label = "ld6:red";
 165             gpios = <&gpio0 79 0>;
 166         };
 167
 168         ld7 {
 169             label = "ld7:red";
 170             gpios = <&gpio0 80 0>;
 171         };
 172     };
 173 };