《8位2级、4级流水线加法器设计》

/*----------------2级流水线-------------------------*/
module add_8(ina,inb,sum_out,clk,rst_n,);
  parameter add_width=8;
  parameter sum_width=9;
  parameter half_add_width=4;
  
  input [add_width-1:0]  ina;
  input [add_width-1:0]  inb;
  input                  clk;
  input                  rst_n;
  
  output [sum_width-1:0] sum_out;
  reg    [sum_width-1:0] sum_out;
  reg    [half_add_width-1:0] ina_lsb;//lsb is the signicifient bit.
  reg    [half_add_width-1:0] ina_msb;
  reg    [half_add_width-1:0] inb_lsb;
  reg    [half_add_width-1:0] inb_msb;
  reg    [half_add_width-1:0] ina_msb1; 
  reg    [half_add_width-1:0] inb_msb1;
  reg    [half_add_width:0] sum11;
  wire   [half_add_width:0] sum1;
  wire   [half_add_width:0] sum2;
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
 ina_lsb<=4'b0000;
 ina_msb<=4'b0000;
 inb_lsb<=4'b0000;
 inb_msb<=4'b0000;
end
    else
   begin
  ina_lsb<=ina[3:0];
ina_msb<=ina[7:4];
inb_lsb<=inb[3:0];
inb_msb<=inb[7:4];
end
  end
  
  add_4 u1(ina_lsb,inb_lsb,1'b0,sum1,clk,rst_n);//底层2位全加器
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
  ina_msb1<=4'b0000;
inb_msb1<=4'b0000;
end
else
   begin
  ina_msb1<=ina_msb;
inb_msb1<=inb_msb;
end
  end
  
  add_4 u2(ina_msb1,inb_msb1,sum1[4],sum2,clk,rst_n);
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   sum11<=4'b0000;
else
   sum11<=sum1;
  end
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
sum_out<=9'b0000_00000;
else
   sum_out<={sum2,sum11[3:0]};
  end
   

endmodule 

/***********4级流水线**************/
module add_8(ina,inb,sum_out,clk,rst_n);
  parameter  add_width=8;
  parameter  sum_width=9;
  parameter half_add_width=2;
  
  input [add_width-1:0]  ina;
  input [add_width-1:0]  inb;
  input                  clk;
  input                  rst_n;
  
  output [sum_width-1:0] sum_out;
  reg    [sum_width-1:0] sum_out;
  
  
  reg    [half_add_width-1:0] ina_lsb1,inb_lsb1;//第1级
  reg    [half_add_width-1:0] ina_lsb2,inb_lsb2;//第2级
  reg    [half_add_width-1:0] ina_msb3,inb_msb3;//第3级
  reg    [half_add_width-1:0] ina_msb4,inb_msb4;//第4级
  
  reg    [half_add_width-1:0] ina_lsbb2,inb_lsbb2;//第2级输入数据寄存器
  reg    [half_add_width-1:0] ina_msbb3,inb_msbb3;//第3级输入数据寄存器
  reg    [half_add_width-1:0] ina_msbb4,inb_msbb4;//第4级输入数据寄存器
 
  wire   [half_add_width:0] sum1;//注意进位，都是3位,模块实例化时，只能是wire类型
  wire   [half_add_width:0] sum2;//注意进位，都是3位
  wire   [half_add_width:0] sum3;//注意进位，都是3位
  wire   [half_add_width:0] sum4;//注意进位，都是3位
   
  reg     [half_add_width:0] sum11;
  reg     [half_add_width:0] sum22;
  reg     [half_add_width:0] sum33;
 
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
  ina_lsb1<=2'b00;
ina_lsb2<=2'b00;
ina_msb3<=2'b00;
ina_msb4<=2'b00;

inb_lsb1<=2'b00;
inb_lsb2<=2'b00;
inb_msb3<=2'b00;
inb_msb4<=2'b00;
   end
else 
   begin
  ina_lsb1<=ina[1:0];
ina_lsb2<=ina[3:2];
ina_msb3<=ina[5:4];
ina_msb4<=ina[7:6];

inb_lsb1<=inb[1:0];
inb_lsb2<=inb[3:2];
inb_msb3<=inb[5:4];
inb_msb4<=inb[7:6];
end   
  end
  
  //第1级
  add_2 u1(ina_lsb1,inb_lsb1,1'b0,sum1,clk,rst_n);//(A,B,Cin,Sum,clk,rst_n);
   
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
  ina_lsbb2<=2'b00;
  inb_lsbb2<=2'b00;
end
else 
   begin
  ina_lsbb2<=ina_lsb2;
  inb_lsbb2<=inb_lsb2;  
end
  end
  //第2级
  add_2 u2(ina_lsbb2,inb_lsbb2,sum1[2],sum2,clk,rst_n);
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
  ina_msbb3<=2'b00;
  inb_msbb3<=2'b00;
end
else 
   begin
  ina_msbb3<=ina_msb3;
  inb_msbb3<=inb_msb3;  
end
  end
  //第3级
  add_2 u3(ina_msbb3,inb_msbb3,sum2[2],sum3,clk,rst_n);
  
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
  ina_msbb4<=2'b00;
  inb_msbb4<=2'b00;
end
else 
   begin
  ina_msbb4<=ina_msb4;
  inb_msbb4<=inb_msb4;  
end
  end
  //第4级
  add_2 u4(ina_msbb4,inb_msbb4,sum3[2],sum4,clk,rst_n);
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   begin
        sum11<=3'b000;
sum22<=3'b000;
sum33<=3'b000;

   end 

  else

   begin
sum11<=sum1;
sum22<=sum2;
sum33<=sum3;
           end
  end
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   sum_out<=9'b0000_00000;
else 
   sum_out<={sum4,sum33[1:0],sum22[1:0],sum11[1:0]};
  end

endmodule*/

2级仿真没有问题，但是4级仿真能计算出正确结果，但是在正确值之前会有乱码，不知道什么原因？感觉这种方法比较明了。哪位帮忙看看？求助、求助、求助

底层模块

module add_2(A,B,Cin,Sum,clk,rst_n);


  parameter add_width=2;
  parameter sum_width=3;
  
  input   [add_width:0] A,B;
  input        Cin;
  input    clk,rst_n;
  output  [sum_width:0]Sum;
  reg     [sum_width:0]Sum;
  
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   Sum<=3'b000;
else 
   Sum<=A+B+Cin;
  end

endmodule

module add_4(A,B,Cin,Sum,clk,rst_n);
  parameter add_width=4;
  parameter sum_width=5;
  input   [add_width-1:0] A,B;
  input        Cin;
  input  clk,rst_n;
  output  [sum_width-1:0]Sum;
  reg     [sum_width-1:0]Sum;
  
  
  always @(posedge clk or negedge rst_n)
  begin
    if(!rst_n)
   Sum<=5'b00000;
else 
   Sum<=A+B+Cin;
  end
endmodule