tessent etchecker步骤(1)

Tessent软件流程分为4步

1. Etchecker

2. Etplaner

3. Etassemble

4. Etsignoff

首先为etchecker步骤,提取设计时钟信息和设计规则检查。

Tessent有两种flow方式,其中一种为makefile方式,根据生成的Makefile文件内提示的步骤一步一步执行,简单方便,且不易出错。

另一种就是脚本方式

Etchecker执行时,

1)首先执行etchecker car -gentemplate ON,产生初始的文件和配置文件,比如makefile、car.etchecker,car.etchecker_README等,然后可以采用两种flow执行etchecker步骤,

2)然后提取时钟信息,脚本为run_etchecker_clocks,内容如下:

etchecker car \

../GATE/CAR/car.v \

../GATE/DASHBOARD/dashboard.v \

../GATE/ENGINE/engine.v \

../GATE/NAVIGATION/navigation.v \

-y ../PLL \

-y ../MEM \

-y ../../Dolphin/tsmc13/lvision \

-y ../../Dolphin/tsmc13/verilog \

-v ../../Dolphin/tsmc13/verilog/pads.v \

+libext+.v \

-memLib ../MEM/*.lvlib \

-mode clockInfo \   #-mode ruleCheck

-padLib ../../Dolphin/tsmc13/lvision/pad.library \

-batch off

本步骤需要配置文件car.etchecker文件,需要在生成初始文件的基础,根据设计需要进行修改。car.etchecker文件需要修改的内容如下:

lv.Target -type Top

lv.EmbeddedTest -bscan On -memory On -logic Off

lv.BlackBoxModule -name PLL

lv.BlackBoxModule -name mode_control -isolation Assume

lv.JTAGOption -pin TDI -option TDI

lv.JTAGOption -pin TDO -option TDO

lv.JTAGOption -pin TRST -option TRST

lv.JTAGOption -pin TMS -option TMS

lv.JTAGOption -pin TCK -option TCK


然后执行source ./run_etchecker_clocks,生成etcheckerInfo文件夹

3)然后设计规则检查,run_etchecker_rules脚本为

etchecker car \

../GATE/CAR/car.v \

../GATE/DASHBOARD/dashboard.v \

../GATE/ENGINE/engine.v \

../GATE/NAVIGATION/navigation.v \

-y ../PLL \

-y ../MEM \

-y ../../Dolphin/tsmc13/lvision \

-y ../../Dolphin/tsmc13/verilog \

-v ../../Dolphin/tsmc13/verilog/pads.v \

+libext+.v \

-memLib ../MEM/*.lvlib \

-padLib ../../Dolphin/tsmc13/lvision/pad.library \

-mode ruleCheck \

-batch off

然后修改配置文件car.etchecker,修改后

lv.Target -type Top

lv.EmbeddedTest -bscan On -memory On -logic Off

lv.BlackBoxModule -name PLL

lv.BlackBoxModule -name mode_control -isolation Assume

lv.JTAGOption -pin TDI -option TDI

lv.JTAGOption -pin TDO -option TDO

lv.JTAGOption -pin TRST -option TRST

lv.JTAGOption -pin TMS -option TMS

lv.JTAGOption -pin TCK -option TCK

lv.ClockDomainBase -pin "car.PLL.VCO_4" -frequency 100 -label CLK100MHz -polarity 1

lv.ClockDomainBase -pin "car.CK33" -frequency 33 -label CLK33MHz -polarity 1

lv.ClockDomainBase -pin "car.CK25" -frequency 25 -label CLK25MHz -polarity 1 -injectPin car.CK25MHz_CLK.A

lv.internalClocksource -pin "car.PLL.VCO_4" -referencePin CK25 -freqRatioRelToPin 4.0

修改完,执行source  ./run_etchecker_rules脚本。

最后查看report文件和log文件,无误,etchecker步骤执行完毕,接下来执行etplanner。

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