基于FPGA的人脸检测(2)

MATLABl利用肤色检测模型工程代码

  • 简述
  • 工程代码
  • 仿真结果

简述

本来打算两篇博客合成一篇博客发布,但是因为CSDN博客字数的限制,这里将肤色检测的代码在该篇博客中给出。

工程代码

这里因为与前面的工程相比,代码变化的比较多,所以我们这里给出整个工程的代码:
top模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : top.v
// Create Time  : 2020-03-01 20:33:42
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module top(
    //System Interfaces
    input                       sclk                    ,
    input                       rst_n                   ,
    //DDR3 Interfaces           
    output  wire    [13:0]      ddr3_addr               ,
    output  wire    [ 2:0]      ddr3_ba                 ,
    output  wire                ddr3_cas_n              ,
    output  wire                ddr3_ck_n               ,
    output  wire                ddr3_ck_p               ,
    output  wire                ddr3_cke                ,
    output  wire                ddr3_ras_n              ,
    output  wire                ddr3_reset_n            ,
    output  wire                ddr3_we_n               ,
    inout           [31:0]      ddr3_dq                 ,
    inout           [ 3:0]      ddr3_dqs_n              ,
    inout           [ 3:0]      ddr3_dqs_p              ,
    output  wire    [ 0:0]      ddr3_cs_n               ,
    output  wire    [ 3:0]      ddr3_dm                 ,
    output  wire    [ 0:0]      ddr3_odt                ,
    //Gigbit Interfaces
    output  wire                phy_rst_n               ,
    input           [ 3:0]      rx_data                 ,
    input                       rx_ctrl                 ,
    input                       rx_clk                  ,
    //USB3 Interfaces
    output  wire                USBSS_EN                ,
    input                       USB_clk                 ,
    inout           [15:0]      data                    ,
    inout           [ 1:0]      be                      ,
    input                       rxf_n                   ,
    input                       txf_n                   ,
    output  wire                oe_n                    ,
    output  wire                wr_n                    ,
    output  wire                siwu_n                  ,
    output  wire                rd_n                    ,
    output  wire                wakeup                  ,
    output  wire    [ 1:0]      gpio                                 
    );
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
//clk_wiz_0_inst
wire                            clk_200m                ;
wire                            locked                  ;
wire                            clk_125m                ; 
//ddr3_drive_inst
wire                            init_calib_complete     ;
wire                            c3_p0_cmd_clk           ;
wire                            c3_p0_cmd_en            ;
wire                [ 2:0]      c3_p0_cmd_instr         ;
wire                [27:0]      c3_p0_cmd_byte_addr     ;
wire                [ 6:0]      c3_p0_cmd_bl            ;
wire                            c3_p0_wr_clk            ;
wire                            c3_p0_wr_en             ;
wire                [31:0]      c3_p0_wr_mask           ;
wire                [255:0]     c3_p0_wr_data           ;
wire                [10:0]      c3_p0_wr_count          ; 

wire                        	c3_p1_cmd_clk           ;
wire                        	c3_p1_cmd_en            ;
wire                [ 2:0]  	c3_p1_cmd_instr         ;
wire                [27:0]  	c3_p1_cmd_byte_addr     ;
wire                [ 6:0]  	c3_p1_cmd_bl            ;
wire                        	c3_p1_rd_clk            ;
wire                        	c3_p1_rd_en             ;
wire                [255:0] 	c3_p1_rd_data           ;
wire                [10:0]  	c3_p1_rd_count          ;

//sensor_data_gen_inst
wire                            clk_24m                 ;
wire                            data_wr_en              ;
wire                [31:0]      data_wr                 ;

//usb3_drive_inst
wire                [15:0]      data_in                 ; 
wire                            data_req                ;

wire                [ 7:0]      image_data              ;
wire                            image_data_en           ;
wire                [31:0]      rlst                    ;     
wire                            rlst_flag               ;

//conver_bit_inst
wire                [10:0]      x_min                   ;        
wire                [10:0]      x_max                   ;        
wire                [10:0]      y_min                   ;        
wire                [10:0]      y_max                   ;        
wire                            po_flag                 ;      

 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
clk_wiz_0 clk_wiz_0_inst(
    // Clock out ports
    .clk_out1                       (clk_200m                       ),     // output clk_out1
    .clk_out2                       (clk_125m                       ),
    .clk_out3                       (clk_50m                        ),
    // Status and control signals
    .reset                          (~rst_n                         ), // input reset
    .locked                         (locked                         ),       // output locked
    // Clock in ports
    .clk_in1                        (sclk                           )
);      // input clk_in1

ddr3_top ddr3_top_inst(
    //System Interfaces
    .rst_n                          (rst_n                          ),
    .locked                         (locked                         ),
    .clk_200m                       (clk_200m                       ), 
    //DDR3 Interfaces           
    .ddr3_addr                      (ddr3_addr                      ),
    .ddr3_ba                        (ddr3_ba                        ),
    .ddr3_cas_n                     (ddr3_cas_n                     ),
    .ddr3_ck_n                      (ddr3_ck_n                      ),
    .ddr3_ck_p                      (ddr3_ck_p                      ),
    .ddr3_cke                       (ddr3_cke                       ),
    .ddr3_ras_n                     (ddr3_ras_n                     ),
    .ddr3_reset_n                   (ddr3_reset_n                   ),
    .ddr3_we_n                      (ddr3_we_n                      ),
    .ddr3_dq                        (ddr3_dq                        ),
    .ddr3_dqs_n                     (ddr3_dqs_n                     ),
    .ddr3_dqs_p                     (ddr3_dqs_p                     ),
    .ddr3_cs_n                      (ddr3_cs_n                      ),
    .ddr3_dm                        (ddr3_dm                        ),
    .ddr3_odt                       (ddr3_odt                       ),
    //User Interfaces
    .init_calib_complete            (init_calib_complete            ),
    .c3_p0_cmd_clk                  (c3_p0_cmd_clk 					),
    .c3_p0_cmd_en                   (c3_p0_cmd_en                   ),
    .c3_p0_cmd_bl                   (c3_p0_cmd_bl                   ),
    .c3_p0_cmd_byte_addr            (c3_p0_cmd_byte_addr            ),
    .c3_p0_cmd_empty                (								),
    .c3_p0_cmd_full                 (								),
    .c3_p0_wr_clk                   (c3_p0_wr_clk                   ),
    .c3_p0_wr_en                    (c3_p0_wr_en                    ),
    .c3_p0_wr_mask                  (c3_p0_wr_mask                  ),
    .c3_p0_wr_data                  (c3_p0_wr_data                  ),
    .c3_p0_wr_full                  (								),
    .c3_p0_wr_empty                 (								),
    .c3_p0_wr_count                 (c3_p0_wr_count                 ),

    .c3_p1_cmd_clk           		('d0							),
    .c3_p1_cmd_en            		('d0							),
    .c3_p1_cmd_bl            		('d0							),
    .c3_p1_cmd_byte_addr     		('d0							),
    .c3_p1_cmd_empty         		(								),
    .c3_p1_cmd_full          		(								),
    .c3_p1_wr_clk            		('d0							),
    .c3_p1_wr_en             		('d0							),
    .c3_p1_wr_mask           		('d0							),
    .c3_p1_wr_data           		('d0							),
    .c3_p1_wr_full           		(								),
    .c3_p1_wr_empty          		(								),
    .c3_p1_wr_count          		(								),

    .c3_p2_cmd_clk           		(c3_p1_cmd_clk                  ),
    .c3_p2_cmd_en            		(c3_p1_cmd_en                   ),
    .c3_p2_cmd_bl            		(c3_p1_cmd_bl                   ),
    .c3_p2_cmd_byte_addr     		(c3_p1_cmd_byte_addr            ),
    .c3_p2_cmd_empty         		(								),
    .c3_p2_cmd_full          		(								),
    .c3_p2_rd_clk            		(c3_p1_rd_clk                   ),
    .c3_p2_rd_en             		(c3_p1_rd_en                    ),
    .c3_p2_rd_data           		(c3_p1_rd_data                  ),
    .c3_p2_rd_full           		(								),
    .c3_p2_rd_empty          		(								),
    .c3_p2_rd_count          		(c3_p1_rd_count    		        ),

    .c3_p3_cmd_clk           		('d0							),
    .c3_p3_cmd_en            		('d0							),
    .c3_p3_cmd_bl            		('d0							),
    .c3_p3_cmd_byte_addr     		('d0							),
    .c3_p3_cmd_empty         		(								),
    .c3_p3_cmd_full          		(								),
    .c3_p3_rd_clk            		('d0							),
    .c3_p3_rd_en             		('d0							),
    .c3_p3_rd_data           		(								),
    .c3_p3_rd_full           		(								),
    .c3_p3_rd_empty          		(								),
    .c3_p3_rd_count                 (								)

);

ddr3_drive ddr3_drive_inst(
    //System Interfaces
    .rst_n                   		(init_calib_complete			    ),
    //DDR3 Interfaces           	
    .c3_p0_cmd_clk           		(c3_p0_cmd_clk           			),
    .c3_p0_cmd_en            		(c3_p0_cmd_en            			),
    .c3_p0_cmd_instr         		(c3_p0_cmd_instr         			),
    .c3_p0_cmd_byte_addr     		(c3_p0_cmd_byte_addr     			),
    .c3_p0_cmd_bl            		(c3_p0_cmd_bl            			),
    .c3_p0_wr_clk            		(c3_p0_wr_clk            			),
    .c3_p0_wr_en             		(c3_p0_wr_en             			),
    .c3_p0_wr_mask           		(c3_p0_wr_mask           			),
    .c3_p0_wr_data           		(c3_p0_wr_data           			),
    .c3_p0_wr_count          		(c3_p0_wr_count          			),

    .c3_p1_cmd_clk           		(c3_p1_cmd_clk           			),
    .c3_p1_cmd_en            		(c3_p1_cmd_en            			),
    .c3_p1_cmd_instr         		(c3_p1_cmd_instr         			),
    .c3_p1_cmd_byte_addr     		(c3_p1_cmd_byte_addr     			),
    .c3_p1_cmd_bl            		(c3_p1_cmd_bl            			),
    .c3_p1_rd_clk            		(c3_p1_rd_clk            			),
    .c3_p1_rd_en             		(c3_p1_rd_en             			),
    .c3_p1_rd_data           		(c3_p1_rd_data           			),
    .c3_p1_rd_count          		(c3_p1_rd_count          			),
    //Write DDR3
    .clk_24m                        (clk_125m                           ),
    .data_wr_en                     (data_wr_en                         ),
    .data_wr                        (data_wr                            ),
    ////Read DDR3
    .USB_clk                        (USB_clk                            ),
    .wr_n                           (data_req                           ),
    .data_in                        (data_in                            )
);

gbit_top gbit_top_inst(
    //System Interfaces
    .clk_50m                        (clk_50m                            ),
    .clk_125m                       (clk_125m                           ),
    .rst_n                          (locked                             ),
    //Gigbit Interfaces
    .phy_rst_n                      (phy_rst_n                          ),
    .rx_data                        (rx_data                            ),
    .rx_ctrl                        (rx_ctrl                            ),
    .rx_clk                         (rx_clk                             ),
    //Communication Interfaces
    .image_data                     (image_data                         ),
    .image_data_en                  (image_data_en                      ),
    .rlst                           (rlst                               ),
    .rlst_flag                      (rlst_flag                          )
);

conver_bit conver_bit_inst(
    //System Interfaces
    .sclk                           (clk_125m                           ),
    .rst_n                          (locked                             ),
    //Gigbit Interfaces
    .image_data                     (image_data                         ),
    .image_data_en                  (image_data_en                      ),
    //Communication Interfaces
    .rgb_data                       ({data_wr[15:8],data_wr[23:16],data_wr[31:24],data_wr[7:0]}     ),
    .rgb_data_en                    (data_wr_en                         ),
    .x_min                          (x_min                              ),
    .x_max                          (x_max                              ),
    .y_min                          (y_min                              ),
    .y_max                          (y_max                              ),
    .po_flag                        (po_flag                            )
); 


//sensor_data_gen sensor_data_gen_inst(
//    .clk                            (clk_24m                            ),
//    .rst_n                          (init_calib_complete                ),
//    .rgb                            ({data_wr[15:0],data_wr[31:16]}     ),
//    .de                             (data_wr_en                         ),
//    .vsync                          (                                   ),
//    .hsync                          (                                   )
//);
//lways @(posedge clk_24m)
//   if(init_calib_complete == 1'b0)
//       data_wr_en      <=      1'b0;
//   else  
//       data_wr_en      <=      1'b1;

//lways @(posedge clk_24m)
//   if(init_calib_complete == 1'b0)
//       data_wr         <=      32'd0;
//   else if(data_wr_en == 1'b1) 
//       data_wr         <=      data_wr + 1'b1;
    

usb3_drive usb3_drive_inst(
    //System Interfaces
    .rst_n                          (init_calib_complete                ),
    //USB3 Interfaces
    .USBSS_EN                       (USBSS_EN                           ),
    .sclk                           (USB_clk                            ),
    .data                           (data                                ),
    .be                             (be                                 ),
    .rxf_n                          (rxf_n                              ),
    .txf_n                          (txf_n                              ),
    .oe_n                           (oe_n                               ),
    .wr_n                           (wr_n                               ),
    .siwu_n                         (siwu_n                             ),
    .rd_n                           (rd_n                               ),
    .wakeup                         (wakeup                             ),
    .gpio                           (gpio                               ),
    //Communication Interfaces
    .data_in                        (data_in                            ),
    .data_req                       (data_req                           ),
    .x_min                          (x_min                              ),
    .x_max                          (x_max                              ),
    .y_min                          (y_min                              ),
    .y_max                          (y_max                              ),
    .po_flag                        (po_flag                            )              
);
 


endmodule

ddr3_top模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : ddr3_top.v
// Create Time  : 2020-02-27 23:16:16
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module ddr3_top(
    //System Interfaces
    input                       rst_n                   ,
    input                       locked                  ,
    input                       clk_200m                , 
    //DDR3 Interfaces           
    output  wire    [13:0]      ddr3_addr               ,
    output  wire    [ 2:0]      ddr3_ba                 ,
    output  wire                ddr3_cas_n              ,
    output  wire                ddr3_ck_n               ,
    output  wire                ddr3_ck_p               ,
    output  wire                ddr3_cke                ,
    output  wire                ddr3_ras_n              ,
    output  wire                ddr3_reset_n            ,
    output  wire                ddr3_we_n               ,
    inout           [31:0]      ddr3_dq                 ,
    inout           [ 3:0]      ddr3_dqs_n              ,
    inout           [ 3:0]      ddr3_dqs_p              ,
    output  wire    [ 0:0]      ddr3_cs_n               ,
    output  wire    [ 3:0]      ddr3_dm                 ,
    output  wire    [ 0:0]      ddr3_odt                ,
    //User Interfaces
    output  wire                init_calib_complete     , 
    input                       c3_p0_cmd_clk           ,
    input                       c3_p0_cmd_en            ,
    input           [ 6:0]      c3_p0_cmd_bl            ,
    input           [27:0]      c3_p0_cmd_byte_addr     ,
    output  wire                c3_p0_cmd_empty         ,
    output  wire                c3_p0_cmd_full          ,
    input                       c3_p0_wr_clk            ,
    input                       c3_p0_wr_en             ,
    input           [31:0]      c3_p0_wr_mask           ,
    input           [255:0]     c3_p0_wr_data           ,
    output  wire                c3_p0_wr_full           ,
    output  wire                c3_p0_wr_empty          ,
    output  wire    [10:0]      c3_p0_wr_count          ,

    input                       c3_p1_cmd_clk           ,
    input                       c3_p1_cmd_en            ,
    input            [ 6:0]     c3_p1_cmd_bl            ,
    input            [27:0]     c3_p1_cmd_byte_addr     ,
    output  wire                c3_p1_cmd_empty         ,
    output  wire                c3_p1_cmd_full          ,
    input                       c3_p1_wr_clk            ,
    input                       c3_p1_wr_en             ,
    input            [31:0]     c3_p1_wr_mask           ,
    input            [255:0]    c3_p1_wr_data           ,
    output  wire                c3_p1_wr_full           ,
    output  wire                c3_p1_wr_empty          ,
    output  wire     [10:0]     c3_p1_wr_count          ,

    input                       c3_p2_cmd_clk           ,
    input                       c3_p2_cmd_en            ,
    input            [ 6:0]     c3_p2_cmd_bl            ,
    input            [27:0]     c3_p2_cmd_byte_addr     ,
    output  wire                c3_p2_cmd_empty         ,
    output  wire                c3_p2_cmd_full          ,
    input                       c3_p2_rd_clk            ,
    input                       c3_p2_rd_en             ,
    output 	wire     [255:0]    c3_p2_rd_data           ,
    output  wire                c3_p2_rd_full           ,
    output  wire                c3_p2_rd_empty          ,
    output  wire     [10:0]     c3_p2_rd_count          ,

    input                       c3_p3_cmd_clk           ,
    input                       c3_p3_cmd_en            ,
    input            [ 6:0]     c3_p3_cmd_bl            ,
    input            [27:0]     c3_p3_cmd_byte_addr     ,
    output  wire                c3_p3_cmd_empty         ,
    output  wire                c3_p3_cmd_full          ,
    input                       c3_p3_rd_clk            ,
    input                       c3_p3_rd_en             ,
    output 	wire     [255:0]    c3_p3_rd_data           ,
    output  wire                c3_p3_rd_full           ,
    output  wire                c3_p3_rd_empty          ,
    output  wire     [10:0]     c3_p3_rd_count          

);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
//mig_7series_0_inst  
wire                [27:0]      app_addr                ;
wire                [ 2:0]      app_cmd                 ;
wire                            app_en                  ;
wire                [255:0]     app_wdf_data            ;
wire                            app_wdf_end             ;
wire                            app_wdf_wren            ;
wire                [255:0]     app_rd_data             ;
wire                            app_rd_data_end         ;
wire                            app_rd_data_valid       ;
wire                            app_rdy                 ;
wire                            app_wdf_rdy             ;
wire                [31:0]      app_wdf_mask            ;
wire                            ui_clk                  ;
wire                            ui_clk_sync_rst         ;
//a7_wr_ctrl_inst1
wire                            app_en_wr1              ;
wire                [ 3:0]      app_cmd_wr1             ;
wire                [27:0]      app_addr_wr1            ;
wire                            app_wdf_wren_wr1        ;
wire                [255:0]     app_wdf_data_wr1        ;
wire                [31:0]      app_wdf_mask_wr1        ;
wire                            app_wdf_end_wr1         ;
wire                            a7_wr_start_wr1         ;
wire                [ 6:0]      a7_wr_bl_wr1             ;        
wire                [27:0]      a7_wr_init_addr_wr1      ; 
wire                [255:0]     a7_wr_data_wr1           ;      
wire                [31:0]      a7_wr_mask_wr1           ;      
wire                            a7_wr_end_wr1            ;       
wire                            a7_wr_req_wr1            ;
//a7_wr_ctrl_inst2   
wire                            app_en_wr2              ;
wire                [ 3:0]      app_cmd_wr2             ;
wire                [27:0]      app_addr_wr2            ;
wire                            app_wdf_wren_wr2        ;
wire                [255:0]     app_wdf_data_wr2        ;
wire                [31:0]      app_wdf_mask_wr2        ;
wire                            app_wdf_end_wr2         ;
wire                            a7_wr_start_wr2         ;
wire                [ 6:0]      a7_wr_bl_wr2             ;        
wire                [27:0]      a7_wr_init_addr_wr2      ; 
wire                [255:0]     a7_wr_data_wr2           ;      
wire                [31:0]      a7_wr_mask_wr2           ;      
wire                            a7_wr_end_wr2            ;       
wire                            a7_wr_req_wr2            ; 
//a7_rd_ctrl_inst1
wire                            app_en_rd1              ;
wire                [ 3:0]      app_cmd_rd1             ;
wire                [27:0]      app_addr_rd1            ;
wire                            app_rd_data_valid_rd1   ;
wire                            a7_rd_start_rd1         ;
wire                [ 6:0]      a7_rd_bl_rd1            ;
wire                [27:0]      a7_rd_init_addr_rd1     ;
wire                [255:0]     a7_rd_data_rd1          ;
wire                            a7_rd_data_valid_rd1    ;
wire                            a7_rd_end_rd1           ;
//a7_rd_ctrl_inst2
wire                            app_en_rd2              ;
wire                [ 3:0]      app_cmd_rd2             ;
wire                [27:0]      app_addr_rd2            ;
wire                            app_rd_data_valid_rd2   ;
wire                            a7_rd_start_rd2         ;
wire                [ 6:0]      a7_rd_bl_rd2            ;
wire                [27:0]      a7_rd_init_addr_rd2     ;
wire                [255:0]     a7_rd_data_rd2          ;
wire                            a7_rd_data_valid_rd2    ;
wire                            a7_rd_end_rd2           ;
//arbit_inst
//wire                            c3_p0_cmd_empty         ;
//wire                            c3_p1_cmd_empty         ;
//wire                            c3_p2_cmd_empty         ;
//wire                            c3_p3_cmd_empty         ;

//rst delay
reg                 [ 5:0]      rst_cnt                 ;

      
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/

always @(posedge clk_200m or negedge rst_n)
    if(rst_n == 1'b0)
        rst_cnt             <=      6'b0;
    else if(locked == 1'b0) 
        rst_cnt             <=      6'b0;
    else if(rst_cnt[5] == 1'b0)
        rst_cnt             <=      rst_cnt + 1'b1;

mig_7series_0 mig_7series_0_inst (
    // Memory interface ports
    .ddr3_addr                      (ddr3_addr                      ),  // output [13:0]      ddr3_addr
    .ddr3_ba                        (ddr3_ba                        ),  // output [2:0]     ddr3_ba
    .ddr3_cas_n                     (ddr3_cas_n                     ),  // output            ddr3_cas_n
    .ddr3_ck_n                      (ddr3_ck_n                      ),  // output [0:0]       ddr3_ck_n
    .ddr3_ck_p                      (ddr3_ck_p                      ),  // output [0:0]       ddr3_ck_p
    .ddr3_cke                       (ddr3_cke                       ),  // output [0:0]        ddr3_cke
    .ddr3_ras_n                     (ddr3_ras_n                     ),  // output            ddr3_ras_n
    .ddr3_reset_n                   (ddr3_reset_n                   ),  // output          ddr3_reset_n
    .ddr3_we_n                      (ddr3_we_n                      ),  // output         ddr3_we_n
    .ddr3_dq                        (ddr3_dq                        ),  // inout [31:0]     ddr3_dq
    .ddr3_dqs_n                     (ddr3_dqs_n                     ),  // inout [3:0]       ddr3_dqs_n
    .ddr3_dqs_p                     (ddr3_dqs_p                     ),  // inout [3:0]       ddr3_dqs_p
    .init_calib_complete            (init_calib_complete            ),  // output           init_calib_complete
    .ddr3_cs_n                      (ddr3_cs_n                      ),  // output [0:0]       ddr3_cs_n
    .ddr3_dm                        (ddr3_dm                        ),  // output [3:0]     ddr3_dm
    .ddr3_odt                       (ddr3_odt                       ),  // output [0:0]        ddr3_odt
    // Application interface ports
    .app_addr                       (app_addr                       ),  // input [27:0]        app_addr
    .app_cmd                        (app_cmd                        ),  // input [2:0]      app_cmd
    .app_en                         (app_en                         ),  // input             app_en
    .app_wdf_data                   (app_wdf_data                   ),  // input [255:0]       app_wdf_data
    .app_wdf_end                    (app_wdf_end                    ),  // input                app_wdf_end
    .app_wdf_wren                   (app_wdf_wren                   ),  // input               app_wdf_wren
    .app_rd_data                    (app_rd_data                    ),  // output [255:0]       app_rd_data
    .app_rd_data_end                (app_rd_data_end                ),  // output           app_rd_data_end
    .app_rd_data_valid              (app_rd_data_valid              ),  // output         app_rd_data_valid
    .app_rdy                        (app_rdy                        ),  // output           app_rdy
    .app_wdf_rdy                    (app_wdf_rdy                    ),  // output           app_wdf_rdy
    .app_sr_req                     (1'b0                           ),  // input         app_sr_req
    .app_ref_req                    (1'b0                           ),  // input            app_ref_req
    .app_zq_req                     (1'b0                           ),  // input         app_zq_req
    .app_sr_active                  (                               ),  // output         app_sr_active
    .app_ref_ack                    (                               ),  // output           app_ref_ack
    .app_zq_ack                     (                               ),  // output            app_zq_ack
    .ui_clk                         (ui_clk                         ),  // output            ui_clk
    .ui_clk_sync_rst                (ui_clk_sync_rst                ),  // output           ui_clk_sync_rst
    .app_wdf_mask                   (app_wdf_mask                   ),  // input [31:0]        app_wdf_mask
    // System Clock Ports
    .sys_clk_i                      (clk_200m                       ),
    .sys_rst                        (locked                         ) // input sys_rst
);
arbit arbit_inst(
    //System Interfaces
    .rst_n                          (init_calib_complete            ),
    //DDR3 Interfaces   
    .ui_clk                         (ui_clk                         ),
    .app_addr                       (app_addr                       ),
    .app_cmd                        (app_cmd                        ),
    .app_en                         (app_en                         ),
    .app_wdf_data                   (app_wdf_data                   ),
    .app_wdf_end                    (app_wdf_end                    ),
    .app_wdf_wren                   (app_wdf_wren                   ),
    .app_rd_data_valid              (app_rd_data_valid              ),
    .app_wdf_mask                   (app_wdf_mask                   ),
    //a7_wr_ctrl_inst1  
    .app_en_wr1                     (app_en_wr1                     ),
    .app_cmd_wr1                    (app_cmd_wr1                    ),
    .app_addr_wr1                   (app_addr_wr1                   ),
    .app_wdf_wren_wr1               (app_wdf_wren_wr1               ),
    .app_wdf_data_wr1               (app_wdf_data_wr1               ),
    .app_wdf_mask_wr1               (app_wdf_mask_wr1               ),
    .app_wdf_end_wr1                (app_wdf_end_wr1                ),
    .a7_wr_start_w1                 (a7_wr_start_wr1                 ),
    .a7_wr_end_wr1                  (a7_wr_end_wr1                  ),
    .c3_p0_cmd_empty                (c3_p0_cmd_empty                ),
    //a7_wr_ctrl_inst1  
    .app_en_wr2                     (app_en_wr2                     ),
    .app_cmd_wr2                    (app_cmd_wr2                    ),
    .app_addr_wr2                   (app_addr_wr2                   ),
    .app_wdf_wren_wr2               (app_wdf_wren_wr2               ),
    .app_wdf_data_wr2               (app_wdf_data_wr2               ),
    .app_wdf_mask_wr2               (app_wdf_mask_wr2               ),
    .app_wdf_end_wr2                (app_wdf_end_wr2                ),
    .a7_wr_start_w2                 (a7_wr_start_wr2                 ),
    .a7_wr_end_wr2                  (a7_wr_end_wr2                  ),
    .c3_p1_cmd_empty                (c3_p1_cmd_empty                ),
    //a7_rd_ctrl_inst1  
    .app_en_rd1                     (app_en_rd1                     ),
    .app_cmd_rd1                    (app_cmd_rd1                    ),
    .app_addr_rd1                   (app_addr_rd1                   ),
    .app_rd_data_valid_rd1          (app_rd_data_valid_rd1          ), 
    .a7_rd_start_rd1                (a7_rd_start_rd1                ),
    .a7_rd_end_rd1                  (a7_rd_end_rd1                  ), 
    .c3_p2_cmd_empty                (c3_p2_cmd_empty                ),           
    //a7_rd_ctrl_inst2  
    .app_en_rd2                     (app_en_rd2                     ),
    .app_cmd_rd2                    (app_cmd_rd2                    ),
    .app_addr_rd2                   (app_addr_rd2                   ),
    .app_rd_data_valid_rd2          (app_rd_data_valid_rd2          ), 
    .a7_rd_start_rd2                (a7_rd_start_rd2                ),
    .a7_rd_end_rd2                  (a7_rd_end_rd2                  ),
    .c3_p3_cmd_empty                (c3_p3_cmd_empty                ) 
);


a7_wr_ctrl a7_wr_ctrl_inst1(
    //System Interfaces
    .rst_n                          (init_calib_complete            ),
    //DDR3 Interfaces
    .ui_clk                         (ui_clk                         ),
    .app_rdy                        (app_rdy                        ),
    .app_wdf_rdy                    (app_wdf_rdy                    ),
    .app_en                         (app_en_wr1                     ),
    .app_cmd                        (app_cmd_wr1                    ),
    .app_addr                       (app_addr_wr1                   ),
    .app_wdf_wren                   (app_wdf_wren_wr1               ),
    .app_wdf_data                   (app_wdf_data_wr1               ),
    .app_wdf_mask                   (app_wdf_mask_wr1               ),
    .app_wdf_end                    (app_wdf_end_wr1                ),
    //Communication Interfaces
    .a7_wr_start                    (a7_wr_start_wr1                ),
    .a7_wr_bl                       (a7_wr_bl_wr1                    ),
    .a7_wr_init_addr                (a7_wr_init_addr_wr1             ),
    .a7_wr_data                     (a7_wr_data_wr1                  ),
    .a7_wr_mask                     (a7_wr_mask_wr1                  ),
    .a7_wr_end                      (a7_wr_end_wr1                   ),
    .a7_wr_req                      (a7_wr_req_wr1                   )           
);

fifo_generator_0 cmd_wr1_fifo (
    .rst                            (~init_calib_complete 			),        // input wire rst
    .wr_clk                         (c3_p0_cmd_clk                  ),  // input wire wr_clk
    .rd_clk                         (ui_clk                         ),  // input wire rd_clk
    .din                            ({c3_p0_cmd_bl,c3_p0_cmd_byte_addr}),        // input wire [38 : 0] din
    .wr_en                          (c3_p0_cmd_en                   ),    // input wire wr_en
    .rd_en                          (a7_wr_start_wr1                ),    // input wire rd_en
    .dout                           ({a7_wr_bl_wr1,a7_wr_init_addr_wr1}),      // output wire [38 : 0] dout
    .full                           (c3_p0_cmd_full                 ),      // output wire full
    .empty                          (c3_p0_cmd_empty                )
);  

fifo_generator_1 data_wr1_fifo (
	.rst 							(~init_calib_complete 			),                      // input wire rst
	.wr_clk							(c3_p0_wr_clk					),                // input wire wr_clk
	.rd_clk							(ui_clk 						),                // input wire rd_clk
	.din 							({c3_p0_wr_mask,c3_p0_wr_data}	),                      // input wire [287 : 0] din
	.wr_en							(c3_p0_wr_en 					),                  // input wire wr_en
	.rd_en							(a7_wr_req_wr1 					),                  // input wire rd_en
	.dout							({a7_wr_mask_wr1,a7_wr_data_wr1}),                    // output wire [287 : 0] dout
	.full							(c3_p0_wr_full 					),                    // output wire full
	.empty 							(c3_p0_wr_empty 				),                  // output wire empty
	.wr_data_count 					(c3_p0_wr_count 				)  // output wire [10 : 0] wr_data_count
);   


a7_wr_ctrl a7_wr_ctrl_inst2(
    //System Interfaces
    .rst_n                          (init_calib_complete            ),
    //DDR3 Interfaces
    .ui_clk                         (ui_clk                         ),
    .app_rdy                        (app_rdy                        ),
    .app_wdf_rdy                    (app_wdf_rdy                    ),
    .app_en                         (app_en_wr2                     ),
    .app_cmd                        (app_cmd_wr2                    ),
    .app_addr                       (app_addr_wr2                   ),
    .app_wdf_wren                   (app_wdf_wren_wr2               ),
    .app_wdf_data                   (app_wdf_data_wr2               ),
    .app_wdf_mask                   (app_wdf_mask_wr2               ),
    .app_wdf_end                    (app_wdf_end_wr2                ),
    //Communication Interfaces
    .a7_wr_start                    (a7_wr_start_wr2                ),
    .a7_wr_bl                       (a7_wr_bl_wr2                    ),
    .a7_wr_init_addr                (a7_wr_init_addr_wr2             ),
    .a7_wr_data                     (a7_wr_data_wr2                  ),
    .a7_wr_mask                     (a7_wr_mask_wr2                  ),
    .a7_wr_end                      (a7_wr_end_wr2                   ),
    .a7_wr_req                      (a7_wr_req_wr2                   )           
);

fifo_generator_0 cmd_wr2_fifo (
    .rst                            (~init_calib_complete 			),        // input wire rst
    .wr_clk                         (c3_p1_cmd_clk                  ),  // input wire wr_clk
    .rd_clk                         (ui_clk                         ),  // input wire rd_clk
    .din                            ({c3_p1_cmd_bl,c3_p1_cmd_byte_addr}),        // input wire [38 : 0] din
    .wr_en                          (c3_p1_cmd_en                   ),    // input wire wr_en
    .rd_en                          (a7_wr_start_wr2                ),    // input wire rd_en
    .dout                           ({a7_wr_bl_wr2,a7_wr_init_addr_wr2}),      // output wire [38 : 0] dout
    .full                           (c3_p1_cmd_full                 ),      // output wire full
    .empty                          (c3_p1_cmd_empty                )
);

fifo_generator_1 data_wr2_fifo (
	.rst 							(~init_calib_complete 			),                      // input wire rst
	.wr_clk							(c3_p1_wr_clk					),                // input wire wr_clk
	.rd_clk							(ui_clk 						),                // input wire rd_clk
	.din 							({c3_p1_wr_mask,c3_p1_wr_data}	),                      // input wire [287 : 0] din
	.wr_en							(c3_p1_wr_en 					),                  // input wire wr_en
	.rd_en							(a7_wr_req_wr2 					),                  // input wire rd_en
	.dout							({a7_wr_mask_wr2,a7_wr_data_wr2}),                    // output wire [287 : 0] dout
	.full							(c3_p1_wr_full 					),                    // output wire full
	.empty 							(c3_p1_wr_empty 				),                  // output wire empty
	.wr_data_count 					(c3_p1_wr_count 				)  // output wire [10 : 0] wr_data_count
);

a7_rd_ctrl a7_rd_ctrl_inst1(
    //System Interfaces
    .rst_n                          (init_calib_complete            ),
    //DDR3 Interfaces   
    .ui_clk                         (ui_clk                         ),
    .app_en                         (app_en_rd1                     ),
    .app_cmd                        (app_cmd_rd1                    ),
    .app_addr                       (app_addr_rd1                   ),
    .app_rd_data                    (app_rd_data                    ),
    .app_rd_data_valid              (app_rd_data_valid_rd1          ),
    .app_rdy                        (app_rdy                        ),
    //Communication Interfaces
    .a7_rd_start                    (a7_rd_start_rd1                ),
    .a7_rd_bl                       (a7_rd_bl_rd1                   ),
    .a7_rd_init_addr                (a7_rd_init_addr_rd1            ),
    .a7_rd_data                     (a7_rd_data_rd1                 ),
    .a7_rd_data_valid               (a7_rd_data_valid_rd1           ),
    .a7_rd_end                      (a7_rd_end_rd1                  )
);

fifo_generator_0 cmd_rd1_fifo (
    .rst                            (~rst_cnt[5]        			),        // input wire rst
    .wr_clk                         (c3_p2_cmd_clk                  ),  // input wire wr_clk
    .rd_clk                         (ui_clk                         ),  // input wire rd_clk
    .din                            ({c3_p2_cmd_bl,c3_p2_cmd_byte_addr}),        // input wire [38 : 0] din
    .wr_en                          (c3_p2_cmd_en                   ),    // input wire wr_en
    .rd_en                          (a7_rd_start_rd1                ),    // input wire rd_en
    .dout                           ({a7_rd_bl_rd1,a7_rd_init_addr_rd1}),      // output wire [38 : 0] dout
    .full                           (c3_p2_cmd_full                 ),      // output wire full
    .empty                          (c3_p2_cmd_empty                )
);

fifo_generator_2 data_rd1_fifo (
  .rst 								(~rst_cnt[5] 			        ),                      // input wire rst
  .wr_clk 							(ui_clk 						),                // input wire wr_clk
  .rd_clk 							(c3_p2_rd_clk 					),                // input wire rd_clk
  .din 								(a7_rd_data_rd1 				),                      // input wire [255 : 0] din
  .wr_en 							(a7_rd_data_valid_rd1 			),                  // input wire wr_en
  .rd_en 							(c3_p2_rd_en 					),                  // input wire rd_en
  .dout 							(c3_p2_rd_data 					),                    // output wire [255 : 0] dout
  .full 							(c3_p2_rd_full 					),                    // output wire full
  .empty 							(c3_p2_rd_empty 				),                  // output wire empty
  .rd_data_count 					(c3_p2_rd_count 				)  // output wire [10 : 0] rd_data_count
);

a7_rd_ctrl a7_rd_ctrl_inst2(
    //System Interfaces
    .rst_n                          (init_calib_complete            ),
    //DDR3 Interfaces   
    .ui_clk                         (ui_clk                         ),
    .app_en                         (app_en_rd2                     ),
    .app_cmd                        (app_cmd_rd2                    ),
    .app_addr                       (app_addr_rd2                   ),
    .app_rd_data                    (app_rd_data                    ),
    .app_rd_data_valid              (app_rd_data_valid_rd2          ),
    .app_rdy                        (app_rdy                        ),
    //Communication Interfaces
    .a7_rd_start                    (a7_rd_start_rd2                ),
    .a7_rd_bl                       (a7_rd_bl_rd2                   ),
    .a7_rd_init_addr                (a7_rd_init_addr_rd2            ),
    .a7_rd_data                     (a7_rd_data_rd2                 ),
    .a7_rd_data_valid               (a7_rd_data_valid_rd2           ),
    .a7_rd_end                      (a7_rd_end_rd2                  )
);

fifo_generator_0 cmd_rd2_fifo (
    .rst                            (~rst_cnt[5] 		            ),        // input wire rst
    .wr_clk                         (c3_p3_cmd_clk                  ),  // input wire wr_clk
    .rd_clk                         (ui_clk                         ),  // input wire rd_clk
    .din                            ({c3_p3_cmd_bl,c3_p3_cmd_byte_addr}),        // input wire [38 : 0] din
    .wr_en                          (c3_p3_cmd_en                   ),    // input wire wr_en
    .rd_en                          (a7_rd_start_rd2                ),    // input wire rd_en
    .dout                           ({a7_rd_bl_rd2,a7_rd_init_addr_rd2}),      // output wire [38 : 0] dout
    .full                           (c3_p3_cmd_full                 ),      // output wire full
    .empty                          (c3_p3_cmd_empty                )
);

fifo_generator_2 data_rd2_fifo (
  .rst 								(~rst_cnt[5]			        ),                      // input wire rst
  .wr_clk 							(ui_clk 						),                // input wire wr_clk
  .rd_clk 							(c3_p3_rd_clk 					),                // input wire rd_clk
  .din 								(a7_rd_data_rd2 				),                      // input wire [255 : 0] din
  .wr_en 							(a7_rd_data_valid_rd2 			),                  // input wire wr_en
  .rd_en 							(c3_p3_rd_en 					),                  // input wire rd_en
  .dout 							(c3_p3_rd_data 					),                    // output wire [255 : 0] dout
  .full 							(c3_p3_rd_full 					),                    // output wire full
  .empty 							(c3_p3_rd_empty 				),                  // output wire empty
  .rd_data_count 					(c3_p3_rd_count 				)  // output wire [10 : 0] rd_data_count
);



endmodule

arbit模块:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/03/01 15:17:14
// Design Name: 
// Module Name: arbit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module arbit(
    //System Interfaces
    input                   rst_n                   ,
    //DDR3 Interfaces   
    input                   ui_clk                  ,
    output  reg     [27:0]  app_addr                ,
    output  reg     [ 2:0]  app_cmd                 ,
    output  reg             app_en                  ,
    output  reg     [255:0] app_wdf_data            ,
    output  reg             app_wdf_end             ,
    output  reg             app_wdf_wren            ,
    input                   app_rd_data_valid       ,
    output  reg     [31:0]  app_wdf_mask            ,
    //a7_wr_ctrl_inst1  
    input                   app_en_wr1              ,
    input           [ 3:0]  app_cmd_wr1             ,
    input           [27:0]  app_addr_wr1            ,
    input                   app_wdf_wren_wr1        ,
    input           [255:0] app_wdf_data_wr1        ,
    input           [31:0]  app_wdf_mask_wr1        ,
    input                   app_wdf_end_wr1         ,
    output  reg             a7_wr_start_w1          ,
    input                   a7_wr_end_wr1           ,
    input                   c3_p0_cmd_empty         ,
    //a7_wr_ctrl_inst1  
    input                   app_en_wr2              ,
    input           [ 3:0]  app_cmd_wr2             ,
    input           [27:0]  app_addr_wr2            ,
    input                   app_wdf_wren_wr2        ,
    input           [255:0] app_wdf_data_wr2        ,
    input           [31:0]  app_wdf_mask_wr2        ,
    input                   app_wdf_end_wr2         ,
    output  reg             a7_wr_start_w2          ,
    input                   a7_wr_end_wr2           ,
    input                   c3_p1_cmd_empty         ,
    //a7_rd_ctrl_inst1  
    input                   app_en_rd1              ,
    input           [ 3:0]  app_cmd_rd1             ,
    input           [27:0]  app_addr_rd1            ,
    output  reg             app_rd_data_valid_rd1   , 
    output  reg             a7_rd_start_rd1         ,
    input                   a7_rd_end_rd1           , 
    input                   c3_p2_cmd_empty         ,           
    //a7_rd_ctrl_inst2  
    input                   app_en_rd2              ,
    input           [ 3:0]  app_cmd_rd2             ,
    input           [27:0]  app_addr_rd2            ,
    output  reg             app_rd_data_valid_rd2   , 
    output  reg             a7_rd_start_rd2         ,
    input                   a7_rd_end_rd2           ,
    input                   c3_p3_cmd_empty          
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter   IDLE    =       6'b000001               ;
parameter   ARBIT   =       6'b000010               ;
parameter   WR1     =       6'b000100               ;
parameter   WR2     =       6'b001000               ;
parameter   RD1     =       6'b010000               ;
parameter   RD2     =       6'b100000               ;

reg                 [ 5:0]  state                   ;
reg                 [ 2:0]  rand_cnt                ;

 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rand_cnt        <=      3'd0;   
    else if(rand_cnt == 3'd3)
        rand_cnt        <=      3'd0;
    else
        rand_cnt        <=      rand_cnt + 1'b1;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        state           <=      IDLE;
    else case(state)
        IDLE    :   state           <=      ARBIT;
        ARBIT   :   if(c3_p0_cmd_empty == 1'b0 && rand_cnt == 3'd0)
                        state           <=      WR1;
                    else if(c3_p1_cmd_empty == 1'b0 && rand_cnt == 3'd1)
                        state           <=      WR2;
                    else if(c3_p2_cmd_empty == 1'b0 && rand_cnt == 3'd2)
                        state           <=      RD1;
                    else if(c3_p3_cmd_empty == 1'b0 && rand_cnt == 3'd3)
                        state           <=      RD2;
                    else
                        state           <=      state;                        
        WR1     :   if(a7_wr_end_wr1 == 1'b1)
                        state           <=      ARBIT;
                    else
                        state           <=      state;                        
        WR2     :   if(a7_wr_end_wr2 == 1'b1)
                        state           <=      ARBIT;
                    else
                        state           <=      state;           
        RD1     :   if(a7_rd_end_rd1 == 1'b1)
                        state           <=      ARBIT;
                    else
                        state           <=      state;                        
        RD2     :   if(a7_rd_end_rd2 == 1'b1)
                        state           <=      ARBIT;
                    else
                        state           <=      state;   
        default :   state           <=      IDLE;
    endcase
    
always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_wr_start_w1      <=      1'b0;   
    else if(state == ARBIT && c3_p0_cmd_empty == 1'b0 && rand_cnt == 3'd0) 
        a7_wr_start_w1      <=      1'b1;
    else
        a7_wr_start_w1      <=      1'b0;   

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_wr_start_w2      <=      1'b0;   
    else if(state == ARBIT && c3_p1_cmd_empty == 1'b0 && rand_cnt == 3'd1) 
        a7_wr_start_w2      <=      1'b1;
    else
        a7_wr_start_w2      <=      1'b0;  
          
always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_rd_start_rd1      <=      1'b0;   
    else if(state == ARBIT && c3_p2_cmd_empty == 1'b0 && rand_cnt == 3'd2) 
        a7_rd_start_rd1      <=      1'b1; 
    else
        a7_rd_start_rd1      <=      1'b0;                      

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_rd_start_rd2      <=      1'b0;   
    else if(state == ARBIT && c3_p3_cmd_empty == 1'b0 && rand_cnt == 3'd3) 
        a7_rd_start_rd2      <=      1'b1; 
    else
        a7_rd_start_rd2      <=      1'b0;        

always @(*)
    case(state)
        WR1     :   begin
                        app_addr                =       app_addr_wr1;       
                        app_cmd                 =       app_cmd_wr1;        
                        app_en                  =       app_en_wr1;         
                        app_wdf_data            =       app_wdf_data_wr1;
                        app_wdf_end             =       app_wdf_end_wr1;
                        app_wdf_wren            =       app_wdf_wren_wr1;
                        app_wdf_mask            =       app_wdf_mask_wr1;
                    end 
        WR2     :   begin   
                        app_addr                =       app_addr_wr2;       
                        app_cmd                 =       app_cmd_wr2;        
                        app_en                  =       app_en_wr2;         
                        app_wdf_data            =       app_wdf_data_wr2;
                        app_wdf_end             =       app_wdf_end_wr2;
                        app_wdf_wren            =       app_wdf_wren_wr2;
                        app_wdf_mask            =       app_wdf_mask_wr2;
                    end     
        RD1     :   begin   
                        app_addr                =       app_addr_rd1;
                        app_cmd                 =       app_cmd_rd1;
                        app_en                  =       app_en_rd1;
                        app_rd_data_valid_rd1   =       app_rd_data_valid;
                    end
        RD2     :   begin
                        app_addr                =       app_addr_rd2;
                        app_cmd                 =       app_cmd_rd2;
                        app_en                  =       app_en_rd2;
                        app_rd_data_valid_rd2   =       app_rd_data_valid;
                    end
        default :   begin
                        app_addr                =       28'd0;      
                        app_cmd                 =       3'd0;       
                        app_en                  =       1'b0;        
                        app_wdf_data            =       256'd0;
                        app_wdf_end             =       1'b0;
                        app_wdf_wren            =       1'b0;
                        app_rd_data_valid_rd1   =       1'b0;
                        app_rd_data_valid_rd2   =       1'b0;
                        app_wdf_mask            =       32'd0;
                    end    
    endcase
    


endmodule

a7_wr_ctrl模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : a7_wr_ctrl.v
// Create Time  : 2020-02-29 22:19:50
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module a7_wr_ctrl(
    //System Interfaces
    input                   rst_n           ,
    //DDR3 Interfaces
    input                   ui_clk          ,
    input                   app_rdy         ,
    input                   app_wdf_rdy     ,
    output  wire            app_en          ,
    output  wire    [ 3:0]  app_cmd         ,
    output  reg     [27:0]  app_addr        ,
    output  wire            app_wdf_wren    ,
    output  wire    [255:0] app_wdf_data    ,
    output  wire    [31:0]  app_wdf_mask    ,
    output  wire            app_wdf_end     ,
    //Communication Interfaces
    input                   a7_wr_start     ,
    input           [ 6:0]  a7_wr_bl        ,
    input           [27:0]  a7_wr_init_addr ,
    input           [255:0] a7_wr_data      ,
    input           [31:0]  a7_wr_mask      ,
    output  reg             a7_wr_end       ,
    output  wire            a7_wr_req                  
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
reg                 [ 6:0]  wr_bl           ;
reg                         wr_flag         ;
reg                 [ 6:0]  bl_cnt          ;
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign  app_en          =       wr_flag && app_rdy && app_wdf_rdy;
assign  app_wdf_end     =       app_en;
assign  app_wdf_wren    =       app_en;
assign  app_wdf_data    =       a7_wr_data;
assign  a7_wr_req       =       app_en;
assign  app_wdf_mask    =       a7_wr_mask;
assign  app_cmd         =       3'd0;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        wr_flag         <=      1'b0;
    else if(bl_cnt == wr_bl && app_en == 1'b1)
        wr_flag         <=      1'b0; 
    else if(a7_wr_start == 1'b1)
        wr_flag         <=      1'b1; 
    
always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        wr_bl           <=      7'd0; 
    else if(a7_wr_start == 1'b1)
        wr_bl           <=      a7_wr_bl;
    else
        wr_bl           <=      wr_bl;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        app_addr        <=      28'd0;
    else if(a7_wr_start == 1'b1)
        app_addr        <=      a7_wr_init_addr;
    else if(app_en == 1'b1)
        app_addr        <=      app_addr + 8;
    else
        app_addr        <=      app_addr;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        bl_cnt          <=      7'd0;
    else if(bl_cnt == wr_bl && app_en == 1'b1 && wr_flag == 1'b1)
        bl_cnt          <=      7'd0;
    else if(wr_flag == 1'b1 && app_en == 1'b1)
        bl_cnt          <=      bl_cnt + 1'b1;
    else
        bl_cnt          <=      bl_cnt;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_wr_end       <=      1'b0;    
    else if(bl_cnt == wr_bl && app_en == 1'b1) 
        a7_wr_end       <=      1'b1;
    else
        a7_wr_end       <=      1'b0;
        
endmodule

a7_rd_ctrl模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : a7_rd_ctrl.v
// Create Time  : 2020-03-01 14:32:05
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module a7_rd_ctrl(
    //System Interfaces
    input                   rst_n               ,
    //DDR3 Interfaces   
    input                   ui_clk              ,
    output  reg             app_en              ,
    output  wire    [ 3:0]  app_cmd             ,
    output  reg     [27:0]  app_addr            ,
    input           [255:0] app_rd_data         ,
    input                   app_rd_data_valid   ,
    input                   app_rdy             ,
    //Communication Interfaces
    input                   a7_rd_start         ,
    input           [ 6:0]  a7_rd_bl            ,
    input           [27:0]  a7_rd_init_addr     ,
    output  reg     [255:0] a7_rd_data          ,
    output  reg             a7_rd_data_valid    ,
    output  reg             a7_rd_end 
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
reg                 [ 6:0]  rd_bl               ;
reg                 [ 6:0]  cmd_cnt             ;
reg                         rd_flag             ;
reg 				[ 6:0] 	data_cnt 			;
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign  app_cmd             =       3'd1;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_bl               <=      7'd0;
    else if(a7_rd_start == 1'b1)
        rd_bl               <=      a7_rd_bl;
    else
        rd_bl               <=      a7_rd_bl;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        app_en              <=      1'b0;
    else if(a7_rd_start == 1'b1)
        app_en              <=      1'b1;
    else if(cmd_cnt == rd_bl && app_rdy == 1'b1)
        app_en              <=      1'b0;
    else
        app_en              <=      app_en;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        cmd_cnt             <=      7'd0;   
    else if(rd_flag == 1'b1 && cmd_cnt == rd_bl && app_rdy == 1'b1)
        cmd_cnt             <=      7'd0;
    else if(rd_flag == 1'b1 && app_rdy == 1'b1 && app_en == 1'b1)
        cmd_cnt             <=      cmd_cnt + 1'b1;
    else
        cmd_cnt             <=      cmd_cnt;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_flag             <=      1'b0;
    else if(a7_rd_start == 1'b1)
        rd_flag             <=      1'b1;
    else if(data_cnt == rd_bl && app_rd_data_valid == 1'b1)
        rd_flag             <=      1'b0;
    else
        rd_flag             <=      rd_flag;
        
always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        app_addr            <=      28'd0;
    else if(a7_rd_start == 1'b1)
        app_addr            <=      a7_rd_init_addr;
    else if(app_en == 1'b1 && app_rdy == 1'b1)
        app_addr            <=      app_addr + 8;
    else
        app_addr            <=      app_addr;

always @(posedge ui_clk)
    a7_rd_data              <=      app_rd_data;

always @(posedge ui_clk) 
    a7_rd_data_valid        <=      app_rd_data_valid;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)
        a7_rd_end           <=      1'b0;
    else if(data_cnt == rd_bl && app_rd_data_valid == 1'b1)
        a7_rd_end           <=      1'b1;
    else
        a7_rd_end           <=      1'b0;

always @(posedge ui_clk or negedge rst_n)
    if(rst_n == 1'b0)            
		data_cnt 			<= 		7'd0;
	else if(data_cnt == rd_bl && rd_flag == 1'b1 && app_rd_data_valid == 1'b1)
		data_cnt 			<= 		7'd0;
	else if(rd_flag == 1'b1 && app_rd_data_valid == 1'b1)
		data_cnt 			<= 		data_cnt + 1'b1;
	else
		data_cnt 			<= 		data_cnt;
			
endmodule

ddr3_drive模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : ddr3_drive.v
// Create Time  : 2020-02-22 11:41:08
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module ddr3_drive(
    //System Interfaces
    input                   rst_n                   ,
    //Write DDR3
    input                   clk_24m                 ,
    input                   data_wr_en              ,
    input           [31:0]  data_wr                 ,
    //Read DDR3
    input                   USB_clk                 ,
    input                   wr_n                    ,
    output  wire    [15:0]  data_in                 ,
    //DDR3 Interfaces
    output                  c3_p0_cmd_clk           ,
    output  reg             c3_p0_cmd_en            ,
    output  wire    [ 2:0]  c3_p0_cmd_instr         ,
    output  reg     [27:0]  c3_p0_cmd_byte_addr     ,
    output  wire    [10:0]  c3_p0_cmd_bl            ,
    output                  c3_p0_wr_clk            ,
    output  reg             c3_p0_wr_en             ,
    output  wire    [31:0]  c3_p0_wr_mask           ,
    output  reg     [255:0] c3_p0_wr_data           ,
    input           [ 6:0]  c3_p0_wr_count          ,

    output                  c3_p1_cmd_clk           ,
    output  reg             c3_p1_cmd_en            ,
    output  wire    [ 2:0]  c3_p1_cmd_instr         ,
    output  reg     [27:0]  c3_p1_cmd_byte_addr     ,
    output  wire    [ 6:0]  c3_p1_cmd_bl            ,
    output                  c3_p1_rd_clk            ,
    output  reg             c3_p1_rd_en             ,
    input           [255:0] c3_p1_rd_data           ,
    input           [10:0]  c3_p1_rd_count                     
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
//parameter   BURST_NUM       =   1048576             ;
parameter   BURST_NUM       =   6144                ;
parameter   BURST_LENFTH    =   7'd15               ;

reg                 [ 3:0]  data_cnt                ;
reg                 [ 6:0]  wr_data_cnt             ;
reg                 [15:0]  bl_cnt                  ;
reg                         wr_n_flag               ;
reg                 [31:0]  usb_data                ;
reg                 [ 3:0]  data_cnt_rd             ;  
reg                 [15:0]  bl_cnt_r                ; 
reg                         rd_first                ;
reg                 [255:0] c3_p1_rd_data_r         ;


 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign  c3_p0_cmd_clk       =       clk_24m;
assign  c3_p0_wr_clk        =       clk_24m;
assign  c3_p0_cmd_instr     =       3'd0;
assign  c3_p0_cmd_bl        =       BURST_LENFTH;
assign  c3_p0_wr_mask       =       32'd0;
assign  data_in             =       wr_n_flag == 1'b0 ? usb_data[31:16] : usb_data[15:0];
assign  c3_p1_cmd_clk       =       USB_clk;
assign  c3_p1_rd_clk        =       USB_clk;
assign  c3_p1_cmd_instr     =       3'd1;
assign  c3_p1_cmd_bl        =       BURST_LENFTH;

always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        data_cnt            <=      4'd0;
    else if(data_cnt == 4'd7 && data_wr_en == 1'b1)
        data_cnt            <=      4'd0;
    else if(data_wr_en == 1'b1)
        data_cnt            <=      data_cnt + 1'b1;
    else
        data_cnt            <=      data_cnt;
      
always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p0_wr_data       <=      256'd0; 
    else if(data_wr_en == 1'b1)
        c3_p0_wr_data       <=      {c3_p0_wr_data[223:0],data_wr};
    else
        c3_p0_wr_data       <=      c3_p0_wr_data;

always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p0_wr_en         <=      1'b0;   
    else if(data_cnt == 4'd7 && data_wr_en == 1'b1)
        c3_p0_wr_en         <=      1'b1;
    else
        c3_p0_wr_en         <=      1'b0;

always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        wr_data_cnt         <=      7'd0;
    else if(wr_data_cnt == BURST_LENFTH && c3_p0_wr_en == 1'b1)
        wr_data_cnt         <=      7'd0;
    else if(c3_p0_wr_en == 1'b1)
        wr_data_cnt         <=      wr_data_cnt + 1'b1;
    else
        wr_data_cnt         <=      wr_data_cnt;
          
always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p0_cmd_en        <=      1'b0;
    else if(wr_data_cnt == BURST_LENFTH && c3_p0_wr_en == 1'b1)
        c3_p0_cmd_en        <=      1'b1;
    else
        c3_p0_cmd_en        <=      1'b0;
            
always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p0_cmd_byte_addr <=      28'd0; 
    else if(bl_cnt == BURST_NUM - 1'b1 && c3_p0_cmd_en == 1'b1) 
        c3_p0_cmd_byte_addr <=      28'd0;
    else if(c3_p0_cmd_en == 1'b1)
        c3_p0_cmd_byte_addr <=      c3_p0_cmd_byte_addr + 'd128;     
        
    
always @(posedge clk_24m or negedge rst_n)
    if(rst_n == 1'b0)
        bl_cnt              <=      16'd0;
    else if(bl_cnt == BURST_NUM - 1'b1 && c3_p0_cmd_en == 1'b1)
        bl_cnt              <=      16'd0;
    else if(c3_p0_cmd_en == 1'b1) 
        bl_cnt              <=      bl_cnt + 1'b1;
    else
        bl_cnt              <=      bl_cnt;
        
always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        wr_n_flag           <=      1'b0;  
    else if(wr_n == 1'b0)
        wr_n_flag           <=      wr_n_flag + 1'b1;
    else
        wr_n_flag           <=      wr_n_flag;

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        data_cnt_rd         <=      4'd0;
    else if(data_cnt_rd == 4'd7 && wr_n_flag == 1'b1 && wr_n == 1'b0)
        data_cnt_rd         <=      4'd0;
    else if(wr_n_flag == 1'b1 && wr_n == 1'b0)
        data_cnt_rd         <=      data_cnt_rd + 1'b1;
    else
        data_cnt_rd         <=      data_cnt_rd;

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_first            <=      1'b0;
    else if(c3_p1_rd_count >= BURST_LENFTH/2 && rd_first == 1'b0) 
        rd_first            <=      1'b1;
    else
        rd_first            <=      rd_first;       
    

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p1_rd_en         <=      1'b0;
    else if(c3_p1_rd_count >= BURST_LENFTH/2 && rd_first == 1'b0)
        c3_p1_rd_en         <=      1'b1;
    else if(data_cnt_rd == 4'd7 && wr_n_flag == 1'b1 && wr_n == 1'b0) 
        c3_p1_rd_en         <=      1'b1;
    else
        c3_p1_rd_en         <=      1'b0;

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p1_cmd_en        <=      1'b0; 
    else if(c3_p1_rd_count <= BURST_LENFTH/2)
        c3_p1_cmd_en        <=      1'b1;
    else
        c3_p1_cmd_en        <=      1'b0;

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p1_cmd_byte_addr <=      28'd0;
    else if(bl_cnt_r == BURST_NUM - 1'b1 && c3_p1_cmd_en == 1'b1) 
        c3_p1_cmd_byte_addr <=      28'd0;
    else if(c3_p1_cmd_en == 1'b1)
        c3_p1_cmd_byte_addr <=      c3_p1_cmd_byte_addr + 128;
    else
        c3_p1_cmd_byte_addr <=      c3_p1_cmd_byte_addr;

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        bl_cnt_r            <=      16'd0;
    else if(bl_cnt_r == BURST_NUM - 1'b1 && c3_p1_cmd_en == 1'b1)
        bl_cnt_r            <=      16'd0;
    else if(c3_p1_cmd_en == 1'b1)
        bl_cnt_r            <=      bl_cnt_r + 1'b1;
    else
        bl_cnt_r            <=      bl_cnt_r;   

always @(posedge USB_clk or negedge rst_n)
    if(rst_n == 1'b0)
        c3_p1_rd_data_r     <=      256'd0;
    else if(c3_p1_rd_en == 1'b1) 
        c3_p1_rd_data_r     <=      c3_p1_rd_data;
    else
        c3_p1_rd_data_r     <=      c3_p1_rd_data_r;
                                                                  
always @(*)
    if(c3_p1_rd_en == 1'b1)
        usb_data            <=      c3_p1_rd_data[255:224];
    else case(data_cnt_rd)
        0       :   usb_data            <=      c3_p1_rd_data_r[255:224];          
        1       :   usb_data            <=      c3_p1_rd_data_r[223:192]; 
        2       :   usb_data            <=      c3_p1_rd_data_r[191:160]; 
        3       :   usb_data            <=      c3_p1_rd_data_r[159:128]; 
        4       :   usb_data            <=      c3_p1_rd_data_r[127:96]; 
        5       :   usb_data            <=      c3_p1_rd_data_r[95:64]; 
        6       :   usb_data            <=      c3_p1_rd_data_r[63:32]; 
        7       :   usb_data            <=      c3_p1_rd_data_r[31:0]; 
        default :   usb_data            <=      32'd0;
    endcase

       
endmodule

gbit_top模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : gbit_top.v
// Create Time  : 2020-03-17 09:43:00
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module gbit_top(
    //System Interfaces
    input                   clk_50m         ,
    input                   clk_125m        ,
    input                   rst_n           ,
    //Gigbit Interfaces
    output  reg             phy_rst_n       ,
    input           [ 3:0]  rx_data         ,
    input                   rx_ctrl         ,
    input                   rx_clk          ,
    //Communication Interfaces
    output  wire    [ 7:0]  image_data      ,
    output  wire            image_data_en   ,
    output  wire    [31:0]  rlst            ,
    output  wire            rlst_flag       
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/

reg                 [20:0]  phy_rst_cnt     ;
wire                        rx_clk_90       ;
//iddr_ctrl_inst
wire                [ 7:0]  gb_rx_data      ;
wire                        gb_rx_data_en   ;
wire                        gb_rx_data_err  ;
//run_clk_ctrl_inst
wire                [ 7:0]  dout_o          ;
wire                        dout_en         ;
wire                [12:0]  latch_max       ;
//image_ctrl_inst

 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/

always @(posedge clk_50m or negedge rst_n)
    if(rst_n == 1'b0)
        phy_rst_cnt         <=      21'd0;
    else if(phy_rst_cnt[20] == 1'b0)
        phy_rst_cnt         <=      phy_rst_cnt + 1'b1;
    else
        phy_rst_cnt         <=      phy_rst_cnt;

always @(posedge clk_50m or negedge rst_n)
    if(rst_n == 1'b0)
        phy_rst_n           <=      1'b0;
    else if(phy_rst_cnt[20] == 1'b1)
        phy_rst_n           <=      1'b1;
    else
        phy_rst_n           <=      phy_rst_n;


clk_wiz_1 clk_wiz_1_inst(
    // Clock out ports
    .clk_out1               (rx_clk_90                  ),     // output clk_out1
    // Clock in ports
    .clk_in1                (rx_clk                     )
);    

//clk_wiz_1 clk_wiz_1_inst(
//    // Clock out ports
//    .clk_out1               (clk_50m                    ),     // output clk_out1
//    .clk_out2               (clk_125m                   ),     // output clk_out2
//    // Status and control signals
//    .reset                  (~rst_n                     ), // input reset
//    .locked                 (locked                     ),       // output locked
//   // Clock in ports
//    .clk_in1                (sclk                       )
//);     
                            
iddr_ctrl iddr_ctrl_inst(
    //System Interfaces
    .rst_n                  (rst_n                     ),
    //Gigabit Interfaces
    .rx_data                (rx_data                    ),
    .rx_ctrl                (rx_ctrl                    ),
    .rx_clk                 (rx_clk_90                  ),
    //Communication Interfaces
    .gb_rx_data             (gb_rx_data                 ),
    .gb_rx_data_en          (gb_rx_data_en              ), 
    .gb_rx_data_err         (gb_rx_data_err             )     
);

run_clk_ctrl run_clk_ctrl_inst(
    //System Interfaces
    .sclk                   (clk_125m                   ),
    .rst_n                  (rst_n                      ),
    //Gigbit Interfaces
    .rx_data                (gb_rx_data                 ),
    .rx_en                  (gb_rx_data_en              ),
    .rx_clk                 (rx_clk_90                  ),
    //Communication Interfaces
    .latch_max              (latch_max                  ),
    .dout_o                 (dout_o                     ),
    .dout_en                (dout_en                    )
);

image_ctrl image_ctrl_inst(
    //System Interfaces
    .sclk                   (clk_125m                   ),
    .rst_n                  (rst_n                      ),
    //Gigbit Interfaces
    .dout_o                 (dout_o                     ),
    .dout_en                (dout_en                    ),
    //Communication Interfaces
    .latch_max              (latch_max                  ),
    .image_data             (image_data                 ),
    .image_data_en          (image_data_en              ),
    .rlst                   (rlst                       ),
    .rlst_flag              (rlst_flag                  )       
);

    

endmodule

iddr_ctrl模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : iddr_ctrl.v
// Create Time  : 2020-03-17 09:21:20
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module iddr_ctrl(
    //System Interfaces
    input                   rst_n               ,
    //Gigabit Interfaces
    input           [ 3:0]  rx_data             ,
    input                   rx_ctrl             ,
    input                   rx_clk              ,
    //Communication Interfaces
    output  reg     [ 7:0]  gb_rx_data          ,
    output  reg             gb_rx_data_en       , 
    output  reg             gb_rx_data_err           
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
wire                [ 7:0]  data                ;
wire                        data_en             ; 
wire                        data_err            ;        
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
IDDR #(
    .DDR_CLK_EDGE           ("OPPOSITE_EDGE"            ), // "OPPOSITE_EDGE", "SAME_EDGE" 
                                                           //    or "SAME_EDGE_PIPELINED" 
    .INIT_Q1                (1'b0                       ), // Initial value of Q1: 1'b0 or 1'b1
    .INIT_Q2                (1'b0                       ), // Initial value of Q2: 1'b0 or 1'b1
    .SRTYPE                 ("SYNC"                     )  // Set/Reset type: "SYNC" or "ASYNC" 
) IDDR_ctrl (
    .Q1                     (data_en                    ), // 1-bit output for positive edge of clock
    .Q2                     (data_err                   ), // 1-bit output for negative edge of clock
    .C                      (rx_clk                     ),   // 1-bit clock input
    .CE                     (1'b1                       ), // 1-bit clock enable input
    .D                      (rx_ctrl                    ),   // 1-bit DDR data input
    .R                      (~rst_n                     ),   // 1-bit reset
    .S                      (1'b0                       )    // 1-bit set
   );


genvar i;
    generate
        for (i = 0; i < 4; i = i+1) begin
            IDDR #(
                .DDR_CLK_EDGE           ("OPPOSITE_EDGE"            ), // "OPPOSITE_EDGE", "SAME_EDGE" 
                                                                       //    or "SAME_EDGE_PIPELINED" 
                .INIT_Q1                (1'b0                       ), // Initial value of Q1: 1'b0 or 1'b1
                .INIT_Q2                (1'b0                       ), // Initial value of Q2: 1'b0 or 1'b1
                .SRTYPE                 ("SYNC"                     )  // Set/Reset type: "SYNC" or "ASYNC" 
            ) IDDR_ctrl (
                .Q1                     (data[i]                    ), // 1-bit output for positive edge of clock
                .Q2                     (data[4+i]                  ), // 1-bit output for negative edge of clock
                .C                      (rx_clk                     ),   // 1-bit clock input
                .CE                     (1'b1                       ), // 1-bit clock enable input
                .D                      (rx_data[i]                 ),   // 1-bit DDR data input
                .R                      (~rst_n                     ),   // 1-bit reset
                .S                      (1'b0                       )    // 1-bit set
            );
      end
   endgenerate
  
always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        gb_rx_data          <=      8'd0;
    else 
        gb_rx_data          <=      data;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        gb_rx_data_err      <=      1'b0;
    else 
        gb_rx_data_err      <=      data_err;

always @(posedge rx_clk or negedge rst_n)
     if(rst_n == 1'b0)
        gb_rx_data_en       <=      1'b0;
     else
        gb_rx_data_en       <=      data_en;

endmodule

run_clk_ctrl模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : run_clk_ctrl.v
// Create Time  : 2020-03-17 21:57:11
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module run_clk_ctrl(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Gigbit Interfaces
    input           [ 7:0]  rx_data         ,
    input                   rx_en           ,
    input                   rx_clk          ,
    //Communication Interfaces
    output  reg     [12:0]  latch_max       ,
    output  wire    [ 7:0]  dout_o          ,
    output  reg             dout_en         
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
reg                 [ 2:0]  cnt_55          ;
reg                         mac_en          ;
reg                         mac_en_dly      ;
reg                 [ 7:0]  rx_data_dly     ;
reg                 [12:0]  rx_cnt          ;
reg                         latch_flag      ;
wire                        rx_clr_flag     ;

reg                         mac_en_r1       ;
reg                         mac_en_r2       ;
reg                         mac_en_r3       ;
reg                         mac_en_r4       ;
reg                         mac_en_r5       ;
reg                         mac_en_r6       ;
reg                         mac_en_r7       ;
reg                         rd_start        ;
reg                         rd_en           ;
reg                 [12:0]  rd_cnt          ;

wire                        full            ;
wire                        empty           ;
wire                [ 9:0]  rd_data_count   ;
wire                [ 9:0]  wr_data_count   ;
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign  rx_clr_flag         =       mac_en && ~mac_en_dly;
always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        cnt_55              <=      3'd0;
    else if(mac_en == 1'b0 && rx_data == 8'h55 && rx_en == 1'b1)
        cnt_55              <=      cnt_55 + 1'b1;
    else if(mac_en == 1'b0 && rx_data == 8'hd5 && rx_en == 1'b1) 
        cnt_55              <=      3'd0;
    else 
        cnt_55              <=      3'd0;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        mac_en              <=      1'b0;
    else if(cnt_55 == 3'd7 && rx_data == 8'hd5 && rx_en == 1'b1) 
        mac_en              <=      1'b1;
    else if(rx_en == 1'b0)
        mac_en              <=      1'b0;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        mac_en_dly          <=      1'b0;
    else if(rx_en == 1'b0)
        mac_en_dly          <=      1'b0;
    else if(mac_en == 1'b1)
        mac_en_dly          <=      1'b1; 
    else 
        mac_en_dly          <=      mac_en_dly;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rx_data_dly         <=      8'd0;
    else
        rx_data_dly         <=      rx_data;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        rx_cnt              <=      13'd0;  
    else if(rx_clr_flag == 1'b1)
        rx_cnt              <=      13'd0;
    else if(mac_en_dly == 1'b1)
        rx_cnt              <=      rx_cnt + 1'b1;
    else
        rx_cnt              <=      13'd0;

always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        latch_flag          <=      1'b0;   
    else if(mac_en_dly == 1'b1 && rx_en == 1'b0)
        latch_flag          <=      1'b1;
    else
        latch_flag          <=      1'b0;          
        
always @(posedge rx_clk or negedge rst_n)
    if(rst_n == 1'b0)
        latch_max           <=      13'h1fff;
    else if(rx_clr_flag == 1'b1)
        latch_max           <=      13'h1fff;
    else if(latch_flag == 1'b1)
        latch_max           <=      rx_cnt - 1'b1;
    else
        latch_max           <=      latch_max;
          
always @(posedge sclk)begin
    mac_en_r1               <=      mac_en_dly;
    mac_en_r2               <=      mac_en_r1;
    mac_en_r3               <=      mac_en_r2;
    mac_en_r4               <=      mac_en_r3;
    mac_en_r5               <=      mac_en_r4;
    mac_en_r6               <=      mac_en_r5;
    mac_en_r7               <=      mac_en_r6;
end

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_start            <=      1'b0;
    else if(mac_en_r7 == 1'b0 && mac_en_r6 == 1'b1)
        rd_start            <=      1'b1;
    else
        rd_start            <=      1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_en               <=      1'b0;
    else if(rd_start == 1'b1)
        rd_en               <=      1'b1;
    else if(mac_en_r5 == 1'b0 && rd_cnt == latch_max) 
        rd_en               <=      1'b0;
    else
        rd_en               <=      rd_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_cnt              <=      13'd0;
    else if(mac_en_r5 == 1'b0 && rd_cnt == latch_max)
        rd_cnt              <=      13'd0;
    else if(rd_en == 1'b1)
        rd_cnt              <=      rd_cnt + 1'b1;
    else
        rd_cnt              <=      rd_cnt;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        dout_en             <=      1'b0;
    else 
        dout_en             <=      rd_en;
      
fifo_generator_3 fifo_generator_3_inst(
  .rst                  (1'b0                   ),        // input wire rst
  .wr_clk               (rx_clk                 ),  // input wire wr_clk
  .rd_clk               (sclk                   ),  // input wire rd_clk
  .din                  (rx_data_dly            ),        // input wire [7 : 0] din
  .wr_en                (mac_en_dly             ),    // input wire wr_en
  .rd_en                (rd_en                  ),    // input wire rd_en
  .dout                 (dout_o                 ),      // output wire [7 : 0] dout
  .full                 (full                   ),      // output wire full
  .empty                (empty                  ),    // output wire empty
  .rd_data_count        (rd_data_count          ),  // output wire [9 : 0] rd_data_count
  .wr_data_count        (wr_data_count          )  // output wire [9 : 0] wr_data_count
); 

 
//========================================================================================\
//*******************************     Debug    **********************************
//========================================================================================/


    

endmodule

image_ctrl模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : image_ctrl.v
// Create Time  : 2020-03-18 10:51:41
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module image_ctrl(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Gigbit Interfaces
    input           [ 7:0]  dout_o          ,
    input                   dout_en         ,
    //Communication Interfaces
    input           [12:0]  latch_max       ,
    output  reg     [ 7:0]  image_data      ,
    output  reg             image_data_en   ,
    output  wire    [31:0]  rlst            ,
    output  reg             rlst_flag              
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
reg                 [12:0]  rd_cnt          ;
reg                 [ 2:0]  cnt_aa          ;
reg                         width_en        ;
reg                         height_en       ;
reg                         height_en_r     ;
reg                 [15:0]  width_data      ;
reg                 [15:0]  height_data     ;
reg                         start_image_en  ;
reg                         image_en        ;

 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_cnt          <=      13'd0;
    else if(dout_en == 1'b1 && rd_cnt == latch_max) 
        rd_cnt          <=      13'd0;
    else if(dout_en == 1'b1)
        rd_cnt          <=      rd_cnt + 1'b1;
    else
        rd_cnt          <=      rd_cnt;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        cnt_aa          <=      3'd0;
    else if(rd_cnt == 'd49 && (dout_o == 8'hfa || dout_o == 8'hf5 || dout_o == 8'hf6))
        cnt_aa          <=      3'd0;
    else if(rd_cnt >= 'd42 && rd_cnt <= 'd48 && dout_o == 8'haa)
        cnt_aa          <=      cnt_aa + 1'b1;
    else
        cnt_aa          <=      3'd0;
   
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        width_en        <=      1'b0;    
    else if(rd_cnt == 'd49 && dout_o == 8'hfa)
        width_en        <=      1'b1;
    else if(rd_cnt == 'd51)
        width_en        <=      1'b0;
    else
        width_en        <=      width_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        height_en       <=      1'b0;
    else if(rd_cnt == 'd51 && width_en == 1'b1)
        height_en       <=      1'b1;
    else if(rd_cnt == 'd53)
        height_en       <=      1'b0;
    else
        height_en       <=      height_en;

always @(posedge sclk)
    height_en_r         <=      height_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        width_data      <=      16'd0;
    else if(width_en == 1'b1)
        width_data      <=      {width_data[7:0],dout_o};
    else
        width_data      <=      width_data;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        height_data     <=      16'd0;
    else if(height_en == 1'b1)
        height_data     <=      {height_data[7:0],dout_o};
    else
        height_data     <=      height_data;
          
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rlst_flag       <=      1'b0;
    else if(height_en_r == 1'b1 && rd_cnt == 'd54)
        rlst_flag       <=      1'b1;
    else
        rlst_flag       <=      1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        start_image_en  <=      1'b0;
    else if(rd_cnt == 'd49 && (dout_o == 8'hf5 || dout_o == 8'hf6)) 
        start_image_en  <=      1'b1;
    else if(rd_cnt == 'd51)
        start_image_en  <=      1'b0;
    else
        start_image_en  <=      start_image_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        image_en        <=      1'b0;
    else if(rd_cnt == 'd51 && start_image_en == 1'b1)
        image_en        <=      1'b1;
    else if(rd_cnt == latch_max - 4)
        image_en        <=      1'b0;
    else
        image_en        <=      image_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        image_data      <=      8'd0;
    else if(image_en == 1'b1)
        image_data      <=      dout_o;
    else
        image_data      <=      8'd0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        image_data_en   <=      1'b0;
    else 
        image_data_en   <=      image_en;    
        
mult_gen_0 mult_gen_0_inst (
  .CLK                  (sclk                       ),  // input wire CLK
  .A                    (width_data                 ),      // input wire [7 : 0] A
  .B                    (height_data                ),      // input wire [7 : 0] B
  .P                    (rlst                       )      // output wire [15 : 0] P
);   
 



endmodule

conver_bit模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : conver_bit.v
// Create Time  : 2020-03-18 17:39:59
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module conver_bit(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Gigbit Interfaces
    input           [ 7:0]  image_data      ,
    input                   image_data_en   ,
    //Communication Interfaces
    output  wire    [31:0]  rgb_data        ,
    output  wire            rgb_data_en     ,
    output  wire    [10:0]  x_min           ,
    output  wire    [10:0]  x_max           ,
    output  wire    [10:0]  y_min           ,
    output  wire    [10:0]  y_max           ,
    output  wire            po_flag         
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter           COL_NUM     =   1024    ;

reg                 [ 1:0]  image_cnt       ;
reg                 [23:0]  data            ;
wire                [ 7:0]  sobel_data      ;
reg                         sobel_data_en   ;
reg                         rd_en           ;
wire                [23:0]  dout            ;
reg                 [10:0]  data_cnt        ;
reg                 [10:0]  rd_cnt          ;

wire                [23:0]  ycbcr_data      ;
wire                        ycbcr_flag      ;
wire                [ 7:0]  face_data       ;   
wire                        face_flag       ;
wire                [ 7:0]  erode_data      ;
wire                        erode_flag      ;
wire                [ 7:0]  pad_data        ;
wire                        pad_flag        ;   
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign      rgb_data        =       {8'h00,dout[7:0],dout[15:8],dout[23:16]};
assign      rgb_data_en     =       rd_en;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        image_cnt           <=      2'b0;
    else if(image_cnt == 2'd2 && image_data_en == 1'b1)
        image_cnt           <=      2'd0;
    else if(image_data_en == 1'b1)
        image_cnt           <=      image_cnt + 1'b1;
    else
        image_cnt           <=      image_cnt;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        data                <=      24'd0;
    else if(image_data_en == 1'b1)
        data                <=      {data[15:0],image_data};
    else
        data                <=      data;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        sobel_data_en       <=      1'b0;
    else if(image_cnt == 2'd2 && image_data_en == 1'b1)
        sobel_data_en       <=      1'b1;
    else
        sobel_data_en       <=      1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        data_cnt            <=      11'd0;
    else if(sobel_data_en == 1'b1 && data_cnt == COL_NUM-1)
        data_cnt            <=      11'd0;
    else if(sobel_data_en == 1'b1) 
        data_cnt            <=      data_cnt + 1'b1;
    else
        data_cnt            <=      data_cnt;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_cnt              <=      11'd0;
    else if(rd_en == 1'b1 && rd_cnt == COL_NUM-1)
        rd_cnt              <=      11'd0;
    else if(rd_en == 1'b1)
        rd_cnt              <=      rd_cnt + 1'b1;
    else
        rd_cnt              <=      rd_cnt;
          
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_en               <=      1'b0;
    else if(rd_en == 1'b1 && rd_cnt == COL_NUM-1)
        rd_en               <=      1'b0;
    else if(sobel_data_en == 1'b1 && data_cnt == COL_NUM-1)
        rd_en               <=      1'b1;
    else
        rd_en               <=      rd_en; 

//sobel sobel_inst(
//    //System Interfaces
//    .sclk                           (sclk                               ),
//    .rst_n                          (rst_n                              ),
//    //Communication Interfaces
//    .rx_data                        (dout                               ),
//    .pi_flag                        (rd_en                              ),
//    .tx_data                        (sobel_data                         ),
//    .po_flag                        (rgb_data_en                        )       
//);

rgb2ycrcb rgb2ycrcb_inst(
    //System Interfaces
    .sclk                           (sclk                               ),
    .rst_n                          (rst_n                              ),
    //Communication Interfaces
    .rgb_data                       (dout                               ),
    .rgb_flag                       (rd_en                              ),
    .ycbcr_data                     (ycbcr_data                         ),
    .ycbcr_flag                     (ycbcr_flag                         )
);

face_test face_test_inst(
    //System Interfaces
    .sclk                           (sclk                               ),
    .rst_n                          (rst_n                              ),
    //Communication Interfaces
    .ycbcr_data                     (ycbcr_data                         ),
    .ycbcr_flag                     (ycbcr_flag                         ),
    .face_data                      (face_data                          ),
    .face_flag                      (face_flag                          )    
);

erode erode_inst(
    //System Interfaces
    .sclk                           (sclk                               ),
    .rst_n                          (rst_n                              ),
    //Communication Interfaces
    .rx_data                        (face_data                          ),
    .pi_flag                        (face_flag                          ),
    .tx_data                        (erode_data                         ),
    .po_flag                        (erode_flag                         ) 
);

pad_image pad_image_inst(
    //System Interfaces
    .sclk                           (sclk                               ),
    .rst_n                          (rst_n                              ),
    //Communication Interfaces
    .rx_data                        (erode_data                         ),
    .rx_flag                        (erode_flag                         ),
    .tx_data                        (pad_data                           ),
    .tx_flag                        (pad_flag                           )
);

face_seek face_seek_inst(
    //System Interfaces
    .sclk                           (sclk                               ),
    .rst_n                          (rst_n                              ),
    //Communication Interfaces
    .rx_data                        (pad_data                           ),
    .pi_flag                        (pad_flag                           ),
    .x_min                          (x_min                              ),
    .x_max                          (x_max                              ),
    .y_min                          (y_min                              ),
    .y_max                          (y_max                              ),
    .po_flag                        (po_flag                            )
);

fifo_generator_5 fifo_generator_5_inst(
    .clk                            (sclk                               ),      // input wire clk
    .srst                           (~rst_n                             ),    // input wire srst
    .din                            ({data[7:0],data[15:8],data[23:16]} ),      // input wire [7 : 0] din
    .wr_en                          (sobel_data_en                      ),  // input wire wr_en
    .rd_en                          (rd_en                              ),  // input wire rd_en
    .dout                           (dout                               ),    // output wire [7 : 0] dout
    .full                           (                                   ),    // output wire full
    .empty                          (                                   )  // output wire empty
);        

endmodule

rgb2ycrcb模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : rgb2ycrcb.v
// Create Time  : 2020-04-11 10:06:18
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module rgb2ycrcb(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [23:0]  rgb_data        ,
    input                   rgb_flag        ,
    output  wire    [23:0]  ycbcr_data      ,
    output  reg             ycbcr_flag      
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
reg                 [15:0]  y_mult_r        ;
reg                 [15:0]  y_mult_g        ;
reg                 [15:0]  y_mult_b        ;
reg                 [15:0]  cb_mult_r       ;
reg                 [15:0]  cb_mult_g       ;
reg                 [15:0]  cb_mult_b       ;
reg                 [15:0]  cr_mult_r       ;
reg                 [15:0]  cr_mult_g       ;
reg                 [15:0]  cr_mult_b       ;
reg                 [15:0]  y_add_data      ;
reg                 [15:0]  cb_add_data     ;
reg                 [15:0]  cr_add_data     ;
reg                 [ 7:0]  y_data          ;
reg                 [ 7:0]  cb_data         ;
reg                 [ 7:0]  cr_data         ;
reg                         ycbcr_flag_r1   ;
reg                         ycbcr_flag_r2   ;


 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign      ycbcr_data  =       {y_data,cb_data,cr_data};  

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        y_mult_r            <=          'd0;        
        y_mult_g            <=          'd0;        
        y_mult_b            <=          'd0;             
    end else begin
        y_mult_r            <=          77 * rgb_data[23:16]; 
        y_mult_g            <=          150 * rgb_data[15:8]; 
        y_mult_b            <=          29 * rgb_data[7:0]; 
    end

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        cb_mult_r           <=          'd0;        
        cb_mult_g           <=          'd0;        
        cb_mult_b           <=          'd0;             
    end else begin
        cb_mult_r           <=          -43 * rgb_data[23:16]; 
        cb_mult_g           <=          -85 * rgb_data[15:8]; 
        cb_mult_b           <=          128 * rgb_data[7:0]; 
    end
    
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        cr_mult_r           <=          'd0;        
        cr_mult_g           <=          'd0;        
        cr_mult_b           <=          'd0;             
    end else begin
        cr_mult_r           <=          128 * rgb_data[23:16]; 
        cr_mult_g           <=          -107 * rgb_data[15:8]; 
        cr_mult_b           <=          -21 * rgb_data[7:0]; 
    end 

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        y_add_data          <=          'd0; 
        cb_add_data         <=          'd0; 
        cr_add_data         <=          'd0;      
    end else begin
        y_add_data          <=          y_mult_r + y_mult_g + y_mult_b;  
        cb_add_data         <=          32768 + cb_mult_r + cb_mult_g + cb_mult_b; 
        cr_add_data         <=          32768 + cr_mult_r + cr_mult_g + cr_mult_b;      
    end 

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        y_data              <=          'd0;        
        cb_data             <=          'd0;
        cr_data             <=          'd0; 
    end else begin
        y_data              <=          y_add_data[15:8];          
        cb_data             <=          cb_add_data[15:8];        
        cr_data             <=          cr_add_data[15:8];         
    end

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        ycbcr_flag_r1       <=          1'b0;
        ycbcr_flag_r2       <=          1'b0;
        ycbcr_flag          <=          1'b0;
    end else begin
        ycbcr_flag_r1       <=          rgb_flag;
        ycbcr_flag_r2       <=          ycbcr_flag_r1;
        ycbcr_flag          <=          ycbcr_flag_r2;
    end
      

endmodule

face_test模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : face_test.v
// Create Time  : 2020-04-11 10:57:34
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module face_test(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [23:0]  ycbcr_data      ,
    input                   ycbcr_flag      ,
    output  reg     [ 7:0]  face_data       ,
    output  reg             face_flag           
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter       CB_LOWER        =           77;
parameter       CB_UPPER        =           127;
parameter       CR_LOWER        =           133;
parameter       CR_UPPER        =           173;
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        face_data               <=          8'd0; 
    else if(ycbcr_data[15:8] > CB_LOWER && ycbcr_data[15:8] < CB_UPPER && ycbcr_data[7:0] > CR_LOWER && ycbcr_data[7:0] < CR_UPPER)
        face_data               <=          8'd255;
    else
        face_data               <=          8'd0;
          
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        face_flag               <=          1'b0;
    else 
        face_flag               <=          ycbcr_flag;

endmodule

erode模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : erode.v
// Create Time  : 2020-04-11 22:40:12
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module erode(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [ 7:0]  rx_data         ,
    input                   pi_flag         ,
    output  reg     [ 7:0]  tx_data         ,
    output  wire            po_flag       
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
wire                [ 7:0]  mat_row1                ;
wire                [ 7:0]  mat_row2                ;
wire                [ 7:0]  mat_row3                ;
wire                [ 7:0]  mat_row4                ;
wire                [ 7:0]  mat_row5                ;
wire                [ 7:0]  mat_row6                ;
wire                [ 7:0]  mat_row7                ;
wire                [ 7:0]  mat_row8                ;
wire                [ 7:0]  mat_row9                ;
wire                [ 7:0]  mat_row10               ;
wire                [ 7:0]  mat_row11               ;
wire                [ 7:0]  mat_row12               ;
wire                [ 7:0]  mat_row13               ;

reg                 [ 7:0]  mat_row1_r[12:0]        ;
reg                 [ 7:0]  mat_row2_r[12:0]        ;
reg                 [ 7:0]  mat_row3_r[12:0]        ;
reg                 [ 7:0]  mat_row4_r[12:0]        ;
reg                 [ 7:0]  mat_row5_r[12:0]        ;
reg                 [ 7:0]  mat_row6_r[12:0]        ;
reg                 [ 7:0]  mat_row7_r[12:0]        ;
reg                 [ 7:0]  mat_row8_r[12:0]        ;
reg                 [ 7:0]  mat_row9_r[12:0]        ;
reg                 [ 7:0]  mat_row10_r[12:0]       ;
reg                 [ 7:0]  mat_row11_r[12:0]       ;
reg                 [ 7:0]  mat_row12_r[12:0]       ;
reg                 [ 7:0]  mat_row13_r[12:0]       ;
wire                        mat_flag                ; 
reg                         mat_flag_r1             ;
reg                         mat_flag_r2             ;
reg                         mat_flag_r3             ;
reg                         mat_flag_r4             ;
reg                         mat_flag_r5             ;
reg                         mat_flag_r6             ;
reg                         mat_flag_r7             ;
reg                         mat_flag_r8             ;
reg                         mat_flag_r9             ;
reg                         mat_flag_r10            ;
reg                         mat_flag_r11            ;
reg                         mat_flag_r12            ;
reg                         mat_flag_r13            ;
reg                         mat_flag_r14            ;
reg                         mat_flag_r15            ;
reg                         mat_flag_r16            ;
reg                         erode_flag1             ;
reg                         erode_flag2             ; 
reg                         erode_flag3             ;
reg                         erode_flag4             ;
reg                         erode_flag5             ;
reg                         erode_flag6             ;
reg                         erode_flag7             ;
reg                         erode_flag8             ;
reg                         erode_flag9             ;
reg                         erode_flag10            ;
reg                         erode_flag11            ;
reg                         erode_flag12            ;
reg                         erode_flag13            ;  
 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign      po_flag             =           mat_flag_r16 && mat_flag_r3;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        mat_row1_r[0]           <=          8'd0;
        mat_row2_r[0]           <=          8'd0;
        mat_row3_r[0]           <=          8'd0;
        mat_row4_r[0]           <=          8'd0;
        mat_row5_r[0]           <=          8'd0;
        mat_row6_r[0]           <=          8'd0;
        mat_row7_r[0]           <=          8'd0;
        mat_row8_r[0]           <=          8'd0;
        mat_row9_r[0]           <=          8'd0;
        mat_row10_r[0]          <=          8'd0;
        mat_row11_r[0]          <=          8'd0;
        mat_row12_r[0]          <=          8'd0;
        mat_row13_r[0]          <=          8'd0;
    end else begin
        mat_row1_r[0]           <=          mat_row1;
        mat_row2_r[0]           <=          mat_row2;
        mat_row3_r[0]           <=          mat_row3;
        mat_row4_r[0]           <=          mat_row4;
        mat_row5_r[0]           <=          mat_row5;
        mat_row6_r[0]           <=          mat_row6;
        mat_row7_r[0]           <=          mat_row7;
        mat_row8_r[0]           <=          mat_row8;
        mat_row9_r[0]           <=          mat_row9;
        mat_row10_r[0]          <=          mat_row10;
        mat_row11_r[0]          <=          mat_row11;
        mat_row12_r[0]          <=          mat_row12;
        mat_row13_r[0]          <=          mat_row13;
    end 

genvar i;
    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row1_r[i]       <=      8'd0;   
                else 
                    mat_row1_r[i]       <=      mat_row1_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row2_r[i]       <=      8'd0;   
                else 
                    mat_row2_r[i]       <=      mat_row2_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row3_r[i]       <=      8'd0;   
                else 
                    mat_row3_r[i]       <=      mat_row3_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row4_r[i]       <=      8'd0;   
                else 
                    mat_row4_r[i]       <=      mat_row4_r[i-1]; 
    endgenerate
    
    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row5_r[i]       <=      8'd0;   
                else 
                    mat_row5_r[i]       <=      mat_row5_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row6_r[i]       <=      8'd0;   
                else 
                    mat_row6_r[i]       <=      mat_row6_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row7_r[i]       <=      8'd0;   
                else 
                    mat_row7_r[i]       <=      mat_row7_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row8_r[i]       <=      8'd0;   
                else 
                    mat_row8_r[i]       <=      mat_row8_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row9_r[i]       <=      8'd0;   
                else 
                    mat_row9_r[i]       <=      mat_row9_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row10_r[i]      <=      8'd0;   
                else 
                    mat_row10_r[i]      <=      mat_row10_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row11_r[i]      <=      8'd0;   
                else 
                    mat_row11_r[i]      <=      mat_row11_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row12_r[i]      <=      8'd0;   
                else 
                    mat_row12_r[i]      <=      mat_row12_r[i-1]; 
    endgenerate

    generate
      for (i=1; i < 13; i=i+1)
          always @(posedge sclk or negedge rst_n)
                if(rst_n == 1'b0)
                    mat_row13_r[i]      <=      8'd0;   
                else 
                    mat_row13_r[i]      <=      mat_row13_r[i-1]; 
    endgenerate

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag1             <=          1'b0;
    else if(mat_row1_r[12] == 255 && mat_row1_r[11] == 255 && mat_row1_r[10] == 255 && mat_row1_r[9] == 255 && mat_row1_r[8] == 255 && mat_row1_r[7] == 255 &&
             mat_row1_r[6] == 255 && mat_row1_r[5] == 255 && mat_row1_r[4] == 255 && mat_row1_r[3] == 255 && mat_row1_r[2] == 255 && mat_row1_r[1] == 255 && mat_row1_r[0] == 255) 
        erode_flag1             <=          1'b1;
    else
        erode_flag1             <=          1'b0;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag2             <=          1'b0;
    else if(mat_row2_r[12] == 255 && mat_row2_r[11] == 255 && mat_row2_r[10] == 255 && mat_row2_r[9] == 255 && mat_row2_r[8] == 255 && mat_row2_r[7] == 255 &&
             mat_row2_r[6] == 255 && mat_row2_r[5] == 255 && mat_row2_r[4] == 255 && mat_row2_r[3] == 255 && mat_row2_r[2] == 255 && mat_row2_r[1] == 255 && mat_row2_r[0] == 255) 
        erode_flag2             <=          1'b1;
    else
        erode_flag2             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag3             <=          1'b0;
    else if(mat_row3_r[12] == 255 && mat_row3_r[11] == 255 && mat_row3_r[10] == 255 && mat_row3_r[9] == 255 && mat_row3_r[8] == 255 && mat_row3_r[7] == 255 &&
             mat_row3_r[6] == 255 && mat_row3_r[5] == 255 && mat_row3_r[4] == 255 && mat_row3_r[3] == 255 && mat_row3_r[2] == 255 && mat_row3_r[1] == 255 && mat_row3_r[0] == 255) 
        erode_flag3             <=          1'b1;
    else
        erode_flag3             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag4             <=          1'b0;
    else if(mat_row4_r[12] == 255 && mat_row4_r[11] == 255 && mat_row4_r[10] == 255 && mat_row4_r[9] == 255 && mat_row4_r[8] == 255 && mat_row4_r[7] == 255 &&
             mat_row4_r[6] == 255 && mat_row4_r[5] == 255 && mat_row4_r[4] == 255 && mat_row4_r[3] == 255 && mat_row4_r[2] == 255 && mat_row4_r[1] == 255 && mat_row4_r[0] == 255) 
        erode_flag4             <=          1'b1;
    else
        erode_flag4             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag5             <=          1'b0;
    else if(mat_row5_r[12] == 255 && mat_row5_r[11] == 255 && mat_row5_r[10] == 255 && mat_row5_r[9] == 255 && mat_row5_r[8] == 255 && mat_row5_r[7] == 255 &&
             mat_row5_r[6] == 255 && mat_row5_r[5] == 255 && mat_row5_r[4] == 255 && mat_row5_r[3] == 255 && mat_row5_r[2] == 255 && mat_row5_r[1] == 255 && mat_row5_r[0] == 255) 
        erode_flag5             <=          1'b1;
    else
        erode_flag5             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag6             <=          1'b0;
    else if(mat_row6_r[12] == 255 && mat_row6_r[11] == 255 && mat_row6_r[10] == 255 && mat_row6_r[9] == 255 && mat_row6_r[8] == 255 && mat_row6_r[7] == 255 &&
             mat_row6_r[6] == 255 && mat_row6_r[5] == 255 && mat_row6_r[4] == 255 && mat_row6_r[3] == 255 && mat_row6_r[2] == 255 && mat_row6_r[1] == 255 && mat_row6_r[0] == 255) 
        erode_flag6             <=          1'b1;
    else
        erode_flag6             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag7             <=          1'b0;
    else if(mat_row7_r[12] == 255 && mat_row7_r[11] == 255 && mat_row7_r[10] == 255 && mat_row7_r[9] == 255 && mat_row7_r[8] == 255 && mat_row7_r[7] == 255 &&
             mat_row7_r[6] == 255 && mat_row7_r[5] == 255 && mat_row7_r[4] == 255 && mat_row7_r[3] == 255 && mat_row7_r[2] == 255 && mat_row7_r[1] == 255 && mat_row7_r[0] == 255) 
        erode_flag7             <=          1'b1;
    else
        erode_flag7             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag8             <=          1'b0;
    else if(mat_row8_r[12] == 255 && mat_row8_r[11] == 255 && mat_row8_r[10] == 255 && mat_row8_r[9] == 255 && mat_row8_r[8] == 255 && mat_row8_r[7] == 255 &&
             mat_row8_r[6] == 255 && mat_row8_r[5] == 255 && mat_row8_r[4] == 255 && mat_row8_r[3] == 255 && mat_row8_r[2] == 255 && mat_row8_r[1] == 255 && mat_row8_r[0] == 255) 
        erode_flag8             <=          1'b1;
    else
        erode_flag8             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag9             <=          1'b0;
    else if(mat_row9_r[12] == 255 && mat_row9_r[11] == 255 && mat_row9_r[10] == 255 && mat_row9_r[9] == 255 && mat_row9_r[8] == 255 && mat_row9_r[7] == 255 &&
             mat_row9_r[6] == 255 && mat_row9_r[5] == 255 && mat_row9_r[4] == 255 && mat_row9_r[3] == 255 && mat_row9_r[2] == 255 && mat_row9_r[1] == 255 && mat_row9_r[0] == 255) 
        erode_flag9             <=          1'b1;
    else
        erode_flag9             <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag10            <=          1'b0;
    else if(mat_row10_r[12] == 255 && mat_row10_r[11] == 255 && mat_row10_r[10] == 255 && mat_row10_r[9] == 255 && mat_row10_r[8] == 255 && mat_row10_r[7] == 255 &&
             mat_row10_r[6] == 255 && mat_row10_r[5] == 255 && mat_row10_r[4] == 255 && mat_row10_r[3] == 255 && mat_row10_r[2] == 255 && mat_row10_r[1] == 255 && mat_row10_r[0] == 255) 
        erode_flag10            <=          1'b1;
    else
        erode_flag10            <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag11            <=          1'b0;
    else if(mat_row11_r[12] == 255 && mat_row11_r[11] == 255 && mat_row11_r[10] == 255 && mat_row11_r[9] == 255 && mat_row11_r[8] == 255 && mat_row11_r[7] == 255 &&
             mat_row11_r[6] == 255 && mat_row11_r[5] == 255 && mat_row11_r[4] == 255 && mat_row11_r[3] == 255 && mat_row11_r[2] == 255 && mat_row11_r[1] == 255 && mat_row11_r[0] == 255) 
        erode_flag11            <=          1'b1;
    else
        erode_flag11            <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag12            <=          1'b0;
    else if(mat_row12_r[12] == 255 && mat_row12_r[11] == 255 && mat_row12_r[10] == 255 && mat_row12_r[9] == 255 && mat_row12_r[8] == 255 && mat_row12_r[7] == 255 &&
             mat_row12_r[6] == 255 && mat_row12_r[5] == 255 && mat_row12_r[4] == 255 && mat_row12_r[3] == 255 && mat_row12_r[2] == 255 && mat_row12_r[1] == 255 && mat_row12_r[0] == 255) 
        erode_flag12            <=          1'b1;
    else
        erode_flag12            <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        erode_flag13            <=          1'b0;
    else if(mat_row13_r[12] == 255 && mat_row13_r[11] == 255 && mat_row13_r[10] == 255 && mat_row13_r[9] == 255 && mat_row13_r[8] == 255 && mat_row13_r[7] == 255 &&
             mat_row13_r[6] == 255 && mat_row13_r[5] == 255 && mat_row13_r[4] == 255 && mat_row13_r[3] == 255 && mat_row13_r[2] == 255 && mat_row13_r[1] == 255 && mat_row13_r[0] == 255) 
        erode_flag13            <=          1'b1;
    else
        erode_flag13            <=          1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        tx_data                 <=          8'd0;
    else if(erode_flag12 == 1'b1 && erode_flag11 == 1'b1 && erode_flag10 == 1'b1 && erode_flag9 == 1'b1 && erode_flag8 == 1'b1 && erode_flag7 == 1'b1 && erode_flag6 == 1'b1 &&
            erode_flag5 == 1'b1  && erode_flag4 == 1'b1 && erode_flag3 == 1'b1 && erode_flag2 == 1'b1 && erode_flag1 == 1'b1 && erode_flag13 == 1'b1) 
        tx_data                 <=          8'd255;
    else
        tx_data                 <=          8'd0;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)begin
        mat_flag_r1             <=          1'b0;         
        mat_flag_r2             <=          1'b0;             
        mat_flag_r3             <=          1'b0;             
        mat_flag_r4             <=          1'b0;             
        mat_flag_r5             <=          1'b0;             
        mat_flag_r6             <=          1'b0;             
        mat_flag_r7             <=          1'b0;             
        mat_flag_r8             <=          1'b0;             
        mat_flag_r9             <=          1'b0;             
        mat_flag_r10            <=          1'b0;
        mat_flag_r11            <=          1'b0;   
        mat_flag_r12            <=          1'b0;                        
        mat_flag_r13            <=          1'b0;                        
        mat_flag_r14            <=          1'b0;                        
        mat_flag_r15            <=          1'b0;                        
        mat_flag_r16            <=          1'b0;                                   
    end else begin
        mat_flag_r1             <=          mat_flag;             
        mat_flag_r2             <=          mat_flag_r1;              
        mat_flag_r3             <=          mat_flag_r2;              
        mat_flag_r4             <=          mat_flag_r3;              
        mat_flag_r5             <=          mat_flag_r4;              
        mat_flag_r6             <=          mat_flag_r5;              
        mat_flag_r7             <=          mat_flag_r6;              
        mat_flag_r8             <=          mat_flag_r7;              
        mat_flag_r9             <=          mat_flag_r8;              
        mat_flag_r10            <=          mat_flag_r9;
        mat_flag_r11            <=          mat_flag_r10;
        mat_flag_r12            <=          mat_flag_r11;
        mat_flag_r13            <=          mat_flag_r12;
        mat_flag_r14            <=          mat_flag_r13;
        mat_flag_r15            <=          mat_flag_r14;
        mat_flag_r16            <=          mat_flag_r15;       
    end 
    

mat_13x13 mat_13x13_inst(
    //System Interfaces
    .sclk                   (sclk                   ),
    .rst_n                  (rst_n                  ),
    //Communication Interfaces
    .rx_data                (rx_data                ),
    .pi_flag                (pi_flag                ),
    .mat_row1               (mat_row1               ),
    .mat_row2               (mat_row2               ),
    .mat_row3               (mat_row3               ),
    .mat_row4               (mat_row4               ),
    .mat_row5               (mat_row5               ),
    .mat_row6               (mat_row6               ),
    .mat_row7               (mat_row7               ),
    .mat_row8               (mat_row8               ),
    .mat_row9               (mat_row9               ),
    .mat_row10              (mat_row10              ),
    .mat_row11              (mat_row11              ),
    .mat_row12              (mat_row12              ),
    .mat_row13              (mat_row13              ),
    .mat_flag               (mat_flag               )

);
endmodule

mat_13x13模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : mat_13x13.v
// Create Time  : 2020-04-11 22:13:48
// Editor       : sublime text3, tab size (2)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module mat_13x13(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [ 7:0]  rx_data         ,
    input                   pi_flag         ,
    output  wire    [ 7:0]  mat_row1        ,
    output  wire    [ 7:0]  mat_row2        ,
    output  wire    [ 7:0]  mat_row3        ,
	  output  wire    [ 7:0]  mat_row4        ,
    output  wire    [ 7:0]  mat_row5        ,
    output  wire    [ 7:0]  mat_row6        ,
	  output  wire    [ 7:0]  mat_row7        ,
    output  wire    [ 7:0]  mat_row8        ,
    output  wire    [ 7:0]  mat_row9        ,
	  output  wire    [ 7:0]  mat_row10       ,
    output  wire    [ 7:0]  mat_row11       ,
    output  wire    [ 7:0]  mat_row12       ,
	  output  wire    [ 7:0]  mat_row13       ,
    output  wire            mat_flag 

);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter           COL_NUM     =   1024    ;
parameter           ROW_NUM     =   768     ;

reg                 [10:0]  col_cnt         ;
reg                 [10:0]  row_cnt         ;
wire 						            wr_en1 			    ;
wire                        wr_en2          ;
wire                        wr_en3          ;
wire 						            wr_en4 			    ;
wire 						            wr_en5 			    ;
wire 						            wr_en6 			    ;
wire 						            wr_en7 			    ;
wire 						            wr_en8 			    ;
wire 						            wr_en9 			    ;
wire 						            wr_en10			    ;
wire 						            wr_en11			    ;
wire 						            wr_en12			    ;
wire 						            wr_en13			    ;
wire                        rd_en1          ;
wire                        rd_en2          ;
wire						            rd_en3 			    ;
wire						            rd_en4 			    ;
wire						            rd_en5 			    ;
wire						            rd_en6 			    ;
wire						            rd_en7 			    ;
wire						            rd_en8 			    ;
wire						            rd_en9 			    ;
wire						            rd_en10			    ;
wire						            rd_en11			    ;
wire						            rd_en12			    ;
wire						            rd_en13			    ;
wire                [ 7:0]  fifo1_rd_data   ;
wire                [ 7:0]  fifo2_rd_data   ;
wire                [ 7:0]  fifo3_rd_data   ;
wire                [ 7:0]  fifo4_rd_data   ;
wire                [ 7:0]  fifo5_rd_data   ;
wire                [ 7:0]  fifo6_rd_data   ;
wire                [ 7:0]  fifo7_rd_data   ;
wire                [ 7:0]  fifo8_rd_data   ;
wire                [ 7:0]  fifo9_rd_data   ;
wire                [ 7:0]  fifo10_rd_data  ;
wire                [ 7:0]  fifo11_rd_data  ;
wire                [ 7:0]  fifo12_rd_data  ;
wire                [ 7:0]  fifo13_rd_data  ;



//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign 		wr_en1 			= 		pi_flag;
assign      wr_en2          =       row_cnt >= 11'd1 ? pi_flag : 1'b0;
assign      wr_en3          =       row_cnt >= 11'd2 ? pi_flag : 1'b0;
assign      wr_en4          =       row_cnt >= 11'd3 ? pi_flag : 1'b0;
assign      wr_en5          =       row_cnt >= 11'd4 ? pi_flag : 1'b0;
assign      wr_en6          =       row_cnt >= 11'd5 ? pi_flag : 1'b0;
assign      wr_en7          =       row_cnt >= 11'd6 ? pi_flag : 1'b0;
assign      wr_en8          =       row_cnt >= 11'd7 ? pi_flag : 1'b0;
assign      wr_en9          =       row_cnt >= 11'd8 ? pi_flag : 1'b0;
assign      wr_en10         =       row_cnt >= 11'd9 ? pi_flag : 1'b0;
assign      wr_en11         =       row_cnt >= 11'd10 ? pi_flag : 1'b0;
assign      wr_en12         =       row_cnt >= 11'd11 ? pi_flag : 1'b0;
assign      wr_en13         =       row_cnt >= 11'd12 ? pi_flag : 1'b0;

assign      rd_en1          =       wr_en2;
assign      rd_en2          =       wr_en3;
assign      rd_en3          =       wr_en4;
assign      rd_en4          =       wr_en5;
assign      rd_en5          =       wr_en6;
assign      rd_en6          =       wr_en7;
assign      rd_en7          =       wr_en8;
assign      rd_en8          =       wr_en9;
assign      rd_en9          =       wr_en10;
assign      rd_en10         =       wr_en11;
assign      rd_en11         =       wr_en12;
assign      rd_en12         =       wr_en13;
assign      rd_en13         =       mat_flag;

assign      mat_flag        =       row_cnt >= 11'd13 ? pi_flag : 1'b0;
assign      mat_row1        =       fifo1_rd_data;
assign      mat_row2        =       fifo2_rd_data;
assign      mat_row3        =       fifo3_rd_data;
assign      mat_row4        =       fifo4_rd_data;
assign      mat_row5        =       fifo5_rd_data;
assign      mat_row6        =       fifo6_rd_data;
assign      mat_row7        =       fifo7_rd_data;
assign      mat_row8        =       fifo8_rd_data;
assign      mat_row9        =       fifo9_rd_data;
assign      mat_row10       =       fifo10_rd_data;
assign      mat_row11       =       fifo11_rd_data;
assign      mat_row12       =       fifo12_rd_data;
assign      mat_row13       =       fifo13_rd_data;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        col_cnt             <=          11'd0;
    else if(col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        col_cnt             <=          11'd0;
    else if(pi_flag == 1'b1)
        col_cnt             <=          col_cnt + 1'b1;
    else
        col_cnt             <=          col_cnt;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        row_cnt             <=          11'd0;
    else if(row_cnt == ROW_NUM-1 && col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        row_cnt             <=          11'd0;
    else if(col_cnt == COL_NUM-1 && pi_flag == 1'b1) 
        row_cnt             <=          row_cnt + 1'b1;


fifo_generator_4 mat_fifo1 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (rx_data                    ),      // input wire [7 : 0] din
  .wr_en            (wr_en1                     ),  // input wire wr_en
  .rd_en            (rd_en1                     ),  // input wire rd_en
  .dout             (fifo1_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);
        
fifo_generator_4 mat_fifo2 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo1_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en2                     ),  // input wire wr_en
  .rd_en            (rd_en2                     ),  // input wire rd_en
  .dout             (fifo2_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);
    
fifo_generator_4 mat_fifo3 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo2_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en3                     ),  // input wire wr_en
  .rd_en            (rd_en3                     ),  // input wire rd_en
  .dout             (fifo3_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);
    
fifo_generator_4 mat_fifo4 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo3_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en4                     ),  // input wire wr_en
  .rd_en            (rd_en4                     ),  // input wire rd_en
  .dout             (fifo4_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo5 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo4_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en5                     ),  // input wire wr_en
  .rd_en            (rd_en5                     ),  // input wire rd_en
  .dout             (fifo5_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo6 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo5_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en6                     ),  // input wire wr_en
  .rd_en            (rd_en6                     ),  // input wire rd_en
  .dout             (fifo6_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo7 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo6_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en7                     ),  // input wire wr_en
  .rd_en            (rd_en7                     ),  // input wire rd_en
  .dout             (fifo7_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo8 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo7_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en8                     ),  // input wire wr_en
  .rd_en            (rd_en8                     ),  // input wire rd_en
  .dout             (fifo8_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo9 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo8_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en9                     ),  // input wire wr_en
  .rd_en            (rd_en9                     ),  // input wire rd_en
  .dout             (fifo9_rd_data              ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo10 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo9_rd_data              ),      // input wire [7 : 0] din
  .wr_en            (wr_en10                    ),  // input wire wr_en
  .rd_en            (rd_en10                    ),  // input wire rd_en
  .dout             (fifo10_rd_data             ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo11 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo10_rd_data             ),      // input wire [7 : 0] din
  .wr_en            (wr_en11                    ),  // input wire wr_en
  .rd_en            (rd_en11                    ),  // input wire rd_en
  .dout             (fifo11_rd_data             ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo12 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo11_rd_data             ),      // input wire [7 : 0] din
  .wr_en            (wr_en12                    ),  // input wire wr_en
  .rd_en            (rd_en12                    ),  // input wire rd_en
  .dout             (fifo12_rd_data             ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

fifo_generator_4 mat_fifo13 (
  .clk              (sclk                       ),      // input wire clk
  .srst             (~rst_n                     ),    // input wire srst
  .din              (fifo12_rd_data             ),      // input wire [7 : 0] din
  .wr_en            (wr_en13                    ),  // input wire wr_en
  .rd_en            (rd_en13                    ),  // input wire rd_en
  .dout             (fifo13_rd_data             ),    // output wire [7 : 0] dout
  .full             (                           ),    // output wire full
  .empty            (                           )  // output wire empty
);

endmodule

pad_image模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : pad_image.v
// Create Time  : 2020-04-08 20:36:48
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module pad_image(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [ 7:0]  rx_data         ,
    input                   rx_flag         ,
    output  reg     [ 7:0]  tx_data         ,
    output  reg             tx_flag         
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter       COL_NUM     =   1024        ;
parameter       ROW_NUM     =   768         ;

reg                         rx_flag_r1      ;
reg                         rx_flag_r2      ;
reg                         rx_flag_r3      ;
reg                         rx_flag_r4      ;
reg                         rx_flag_r5      ;
reg                         rx_flag_r6      ;
reg                         rx_flag_r7      ;
reg                         rx_flag_r8      ;
reg                         rx_flag_r9      ;
reg                         rx_flag_r10     ;
reg                         rx_flag_r11     ;
reg                         rx_flag_r12     ;
reg                         rx_flag_r13     ;

 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
always @(posedge sclk)begin
    rx_flag_r1          <=      rx_flag;
    rx_flag_r2          <=      rx_flag_r1;
    rx_flag_r3          <=      rx_flag_r2;      
    rx_flag_r4          <=      rx_flag_r3;      
    rx_flag_r5          <=      rx_flag_r4;      
    rx_flag_r6          <=      rx_flag_r5;      
    rx_flag_r7          <=      rx_flag_r6;      
    rx_flag_r8          <=      rx_flag_r7;      
    rx_flag_r9          <=      rx_flag_r8;      
    rx_flag_r10         <=      rx_flag_r9;     
    rx_flag_r11         <=      rx_flag_r10;     
    rx_flag_r12         <=      rx_flag_r11;     
    rx_flag_r13         <=      rx_flag_r12;     
end

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        tx_data         <=      8'd0; 
    else if(rx_flag == 1'b1)
        tx_data         <=      rx_data;
    else
        tx_data         <=      8'd0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        tx_flag         <=      1'b0;
    else if(rx_flag == 1'b1 || rx_flag_r13 == 1'b1)
        tx_flag         <=      1'b1;
    else
        tx_flag         <=      1'b0;

endmodule

face_seek模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : face_seek.v
// Create Time  : 2020-04-13 22:47:21
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************

module face_seek(
    //System Interfaces
    input                   sclk            ,
    input                   rst_n           ,
    //Communication Interfaces
    input           [ 7:0]  rx_data         ,
    input                   pi_flag         ,
    output  reg     [10:0]  x_min           ,
    output  reg     [10:0]  x_max           ,
    output  reg     [10:0]  y_min           ,
    output  reg     [10:0]  y_max           ,
    output  reg             po_flag         
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter           ROW_NUM     =   768-13  ;
parameter           COL_NUM     =   1024    ; 

reg                 [10:0]  row_cnt         ;
reg                 [10:0]  col_cnt         ;

//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        col_cnt             <=              11'd0;        
    else if(col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        col_cnt             <=              11'd0;
    else if(pi_flag == 1'b1)
        col_cnt             <=              col_cnt + 1'b1;
    else
        col_cnt             <=              col_cnt;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        row_cnt             <=              11'd0;
    else if(row_cnt == ROW_NUM-1 && col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        row_cnt             <=              11'd0;
    else if(col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        row_cnt             <=              row_cnt + 1'b1;
    else
        row_cnt             <=              row_cnt;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        po_flag             <=              1'b0;
    else if(row_cnt == ROW_NUM-1 && col_cnt == COL_NUM-1 && pi_flag == 1'b1)
        po_flag             <=              1'b1;
    else
        po_flag             <=              1'b0;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        x_min               <=              11'd1023;
    else if(po_flag == 1'b1)
        x_min               <=              11'd1023;
    else if(rx_data > 0 && pi_flag == 1'b1 && x_min > col_cnt)
        x_min               <=              col_cnt;
    else
        x_min               <=              x_min;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        x_max               <=              11'd0;
    else if(po_flag == 1'b1)
        x_max               <=              11'd0;
    else if(rx_data > 0 && pi_flag == 1'b1 && x_max < col_cnt)
        x_max               <=              col_cnt;
    else
        x_max               <=              x_max;
          
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        y_min               <=              11'd755;          
    else if(po_flag == 1'b1)
        y_min               <=              11'd755;
    else if(rx_data > 0 && pi_flag == 1'b1 && y_min > row_cnt)
        y_min               <=              row_cnt;
    else
        y_min               <=              y_min;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        y_max               <=              11'd0;
    else if(po_flag == 1'b1)
        y_max               <=              11'd0;
    else if(rx_data > 0 && pi_flag == 1'b1 && y_max < row_cnt)
        y_max               <=              row_cnt;
    else
        y_max               <=              y_max;


endmodule

usb3_drive模块:

`timescale 1ns / 1ps
// *********************************************************************************
// Project Name : OSXXXX
// Author       : zhangningning
// Email        : [email protected]
// Website      : 
// Module Name  : usb3_drive.v
// Create Time  : 2020-03-03 10:36:21
// Editor       : sublime text3, tab size (4)
// CopyRight(c) : All Rights Reserved
//
// *********************************************************************************
// Modification History:
// Date             By              Version                 Change Description
// -----------------------------------------------------------------------
// XXXX       zhangningning          1.0                        Original
//  
// *********************************************************************************
module usb3_drive(
    input                       rst_n               ,
    output  wire                USBSS_EN            ,
    input                       sclk                ,
    inout           [15:0]      data                ,
    inout           [ 1:0]      be                  ,
    input                       rxf_n               ,
    input                       txf_n               ,
    output  reg                 oe_n                ,
    output  reg                 wr_n                ,
    output  wire                siwu_n              ,
    output  reg                 rd_n                ,
    output  wire                wakeup              ,
    output  wire    [ 1:0]      gpio                ,
    //Communication Interfaces
    input           [15:0]      data_in             ,
    output  wire                data_req            ,
    input           [10:0]      x_min               ,        
    input           [10:0]      x_max               ,        
    input           [10:0]      y_min               ,        
    input           [10:0]      y_max               ,        
    input                       po_flag                     
);
 
//========================================================================================\
//**************Define Parameter and  Internal Signals**********************************
//========================================================================================/
parameter   COL_NUM     =       1024*2              ;
parameter   ROW_NUM     =       768                 ;


parameter   IDLE        =       4'b0001             ;
parameter   JUDGE       =       4'b0010             ;
parameter   READ        =       4'b0100             ;
parameter   WRITE       =       4'b1000             ;

reg                 [ 3:0]      state               ;
wire                            fifo_wr             ;
wire                [15:0]      data_wr             ;

reg                 [12:0]      col_cnt             ;
reg                 [12:0]      row_cnt             ;

reg                 [10:0]      x_min_r             ;        
reg                 [10:0]      x_max_r             ;        
reg                 [10:0]      y_min_r             ;        
reg                 [10:0]      y_max_r             ;  
reg                 [15:0]      data_o              ;           


 
//========================================================================================\
//**************     Main      Code        **********************************
//========================================================================================/
assign      USBSS_EN    =       1'b1;
assign      wakeup      =       1'b1;
assign      siwu_n      =       1'b0;
assign      gpio        =       2'b00;    
assign      fifo_wr     =       (rd_n == 1'b0) && (rxf_n == 1'b0);
assign      data_wr     =       (state == READ) ? data : 16'hzzzz;
assign      data_req    =       ~((wr_n == 1'b0) && (txf_n == 1'b0));
assign      data        =       (data_req == 1'b0) ? data_o : 16'hzzzz;
assign      be          =       (state == WRITE) ? 2'b11 : 2'bzz;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        state       <=          IDLE;
    else case(state)
        IDLE    :   state       <=          JUDGE;
        JUDGE   :   if(rxf_n == 1'b0)
                        state       <=          READ;
                    else if(txf_n == 1'b0)
                        state       <=          WRITE;
                    else
                        state       <=          JUDGE;                        
        WRITE   :   if(txf_n == 1'b1)
                        state       <=          JUDGE;
                    else
                        state       <=          WRITE;                        
        READ    :   if(rxf_n == 1'b1)
                        state       <=          JUDGE;
                    else
                        state       <=          READ;
        default :   state       <=          IDLE;
    endcase

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        oe_n        <=          1'b1;     
    else if(state == READ && rxf_n == 1'b1)
        oe_n        <=          1'b1;
    else if(state == READ)
        oe_n        <=          1'b0;
    else
        oe_n        <=          oe_n;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        rd_n        <=          1'b1;
    else if(state == READ && rxf_n == 1'b1)
        rd_n        <=          1'b1;
    else if(state == READ && oe_n == 1'b0)
        rd_n        <=          1'b0;
    else
        rd_n        <=          rd_n;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        wr_n        <=          1'b1;
    else if(state == WRITE && txf_n == 1'b1)
        wr_n        <=          1'b1;
    else if(state == WRITE)
        wr_n        <=          1'b0;
    else
        wr_n        <=          wr_n;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        col_cnt     <=          13'd0;
    else if(data_req == 1'b0 && col_cnt == COL_NUM-1)
        col_cnt     <=          13'd0;
    else if(data_req == 1'b0)
        col_cnt     <=          col_cnt + 1'b1;
    else
        col_cnt     <=          col_cnt;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        row_cnt     <=          13'd0;
    else if(row_cnt == ROW_NUM-1 && data_req == 1'b0 && col_cnt == COL_NUM-1)
        row_cnt     <=          13'd0;
    else if(data_req == 1'b0 && col_cnt == COL_NUM-1)
        row_cnt     <=          row_cnt + 1'b1;
    else
        row_cnt     <=          row_cnt;
        
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        x_min_r     <=          COL_NUM - 1'b1;
    else if(po_flag == 1'b1)
        x_min_r     <=          x_min;
    else
        x_min_r     <=          x_min_r;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        x_max_r     <=          0;
    else if(po_flag == 1'b1)
        x_max_r     <=          x_max;
    else
        x_max_r     <=          x_max_r;          
    
always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        y_min_r     <=          ROW_NUM - 1'b1;
    else if(po_flag == 1'b1)
        y_min_r     <=          y_min;
    else
        y_min_r     <=          y_min_r;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        y_max_r     <=          0;
    else if(po_flag == 1'b1)
        y_max_r     <=          y_max;
    else
        y_max_r     <=          y_max_r; 
          
always @(*)
    if(row_cnt == y_min_r && col_cnt >= x_min_r*2 && col_cnt < x_max_r*2)
        data_o      <=          16'hffff;
    else if(row_cnt == y_max_r && col_cnt >= x_min_r*2 && col_cnt < x_max_r*2)      
        data_o      <=          16'hffff;
    else if((col_cnt >= x_min_r*2 && col_cnt < (x_min_r+1)*2) && row_cnt >= y_min_r && row_cnt < y_max_r) 
        data_o      <=          16'hffff; 
    else if((col_cnt >= x_max_r*2 && col_cnt < (x_max_r+1)*2) && row_cnt >= y_min_r && row_cnt < y_max_r)
        data_o      <=          16'hffff;
    else if(row_cnt == y_min_r && col_cnt >= x_min_r*2 && col_cnt < x_max_r*2)
        data_o      <=          16'hffff;
    else if(row_cnt == y_max_r && col_cnt >= x_min_r*2 && col_cnt < x_max_r*2)      
        data_o      <=          16'hffff;
    else  
        data_o      <=          data_in;

//========================================================================================\
//*******************************     Debug    **********************************
//========================================================================================/
ila_0 ila_0_inst (
    .clk                    (sclk                       ), // input wire clk


    .probe0                 (x_min_r                    ), // input wire [10:0]  probe0  
    .probe1                 (x_max_r                    ), // input wire [10:0]  probe1 
    .probe2                 (y_min_r                    ), // input wire [10:0]  probe2 
    .probe3                 (y_max_r                    ), // input wire [10:0]  probe3 
    .probe4                 (po_flag                    ), // input wire [0:0]  probe4 
    .probe5                 (row_cnt                    ), // input wire [12:0]  probe5 
    .probe6                 (col_cnt                    ), // input wire [12:0]  probe6 
    .probe7                 (data_o                     ) // input wire [15:0]  probe7
);


endmodule

整个项目的工程代码到这里就结束了。

仿真结果

千兆网上位机发送图片:
基于FPGA的人脸检测(2)_第1张图片
USB上位机显示图片:

从上面结果可以看出,虽然图片有点瑕疵,但是人脸定位完全正确。这里图片的瑕疵依然猜测是上位机的原因。前面的文章中已经进行了解释,这里不再深究。

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