Verilog HDL之实用技巧总结

1、驱动时钟的产生

always @(posedge sys_clk or negedge rst_n) 
begin
    if(!rst_n) 
		clk_cnt <= 16'd0;
    else if(clk_cnt >= clk_divide -1'd1) //注意：若spi_div为input类型数据则不可在此减1
		clk_cnt <= 16'd0;
    else
		clk_cnt <= clk_cnt + 1'b1;
end

wire dri_clk = (clk_cnt == (clk_divide-1) ) ? 1: 0;
//dri_clk 信号的频率是dri_clk  speed = clk speed /clk_divide 占空比并非50%

always @(posedge CLK or negedge RST_N) 
begin
    if(!RST_N) 
		begin
			dri_clk <=  1'b1;
			clk_cnt <= 10'd0;
		end
    else if(clk_cnt == clk_divide - 1'd1) 	//F=50M/(clk_divide*2)占空比50%
		begin
			clk_cnt <= 10'd0;
			dri_clk <= ~dri_clk;
		end
    else
        clk_cnt <= clk_cnt + 1'b1;
end

2、信号延迟操作

reg [2:0]	vga_vs_delay;				//VGA行同步信号延迟拍数
reg [2:0]	vga_hs_delay;				//VGA场同步信号延迟拍数
reg [2:0]	vga_data_en_delay;			//VGA数据使能信号延迟拍数
//delay
always @(posedge clk or negedge rst_n) 
begin
	if(!rst_n)
	begin
		vga_vs_delay 		<= 3'd0;
		vga_hs_delay 		<= 3'd0;
		vga_data_en_delay 	<= 3'd0;
	end
	else
	begin
		vga_vs_delay  		<= {vga_vs_delay[1:0],vga_vs};
		vga_hs_delay   		<= {vga_hs_delay[1:0],vga_hs};
		vga_data_en_delay 	<= {vga_data_en_delay[1:0],vga_data_en};
	end
end