ZYNQ: VDMA + VTC +AXI4-Stream to Video Out 调试

 

AXI4-Stream to Video Out 的 locked 锁不住信号解决方案：

 

 

Description

An Issue can arise in Video designs where the AXI4-Stream to Video Out does not lock.

This article lists general guideline on how to debug this problem.

Solution

In situations where the AXI4 Lite interface is available for the AXI4-Stream to Video Out, the core can be reset or enabled through this software.

FID should be grounded for non-interlaced images. 

If the core is not properly reset, there will not be output signals.

When the Video Data path includes VDMA:
 

• AXI4-Stream to Video Out should be set to Master.
   
• mm2s_HSIZE and mm2s_Stride in the VDMA should be set to bytes per line, not pixels per line.

 

When the Video Data path contains Video Scaler IP:

• Ensure the input frame size of AXI4-Stream to Video Out is correct.
   
• Ensure that the Clock frequency is fast enough to give Video Scaler enough time to process pixels.

 

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