STM32CubeMX学习笔记——STM32H743_DRAM

Github

https://github.com/HaHaHaHaHaGe/Planof2019_half/tree/master/Course_Project/STM32H7/Class05_SDRAM

功能简述

移植原子的W9825G6KH初始化、读写函数并配合STM32CubeMX的测试项目，可以进行读写

STM32CubeMX配置

STM32CubeMX版本：4.27.0
配置流程：
Pinout界面选择并开启FMC与RCC
Clock Configuration配置时钟树
Configuration界面配置System
生成工程

Pinout配置

根据芯片进行合适的配置

Clock Configuration配置

开启系统时钟,

Configuration

左侧主要系统功能的开启，或中间软件层功能的开启（如：RTOS、JPEG解码器，文件系统等）
右侧是系统及外设模块的具体配置

FMC

代码部分

main.c

USER CODE BEGIN 0 、USER CODE BEGIN Includes中的代码源自原子的H7中DRAM中的部分驱动代码

/* USER CODE BEGIN Includes */
#define Bank5_SDRAM_ADDR    ((unsigned int)(0XC0000000)) 
#define SDRAM_MODEREG_BURST_LENGTH_1             ((unsigned int)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2             ((unsigned int)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4             ((unsigned int)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8             ((unsigned int)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((unsigned int)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((unsigned int)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2              ((unsigned int)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3              ((unsigned int)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((unsigned int)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((unsigned int)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((unsigned int)0x0200)
/* USER CODE END Includes */
/* USER CODE BEGIN 0 */
unsigned char SDRAM_Send_Cmd(unsigned char bankx,unsigned char cmd,unsigned char refresh,unsigned int regval)
{
    unsigned int target_bank=0;
    FMC_SDRAM_CommandTypeDef Command;
    if(bankx==0) target_bank=FMC_SDRAM_CMD_TARGET_BANK1;       
    else if(bankx==1) target_bank=FMC_SDRAM_CMD_TARGET_BANK2;   
    Command.CommandMode=cmd;              
    Command.CommandTarget=target_bank;     
    Command.AutoRefreshNumber=refresh;    
    Command.ModeRegisterDefinition=regval; 
    if(HAL_SDRAM_SendCommand(&hsdram1,&Command,0XFFFF)==HAL_OK)
    {
        return 0;  
    }
    else return 1;    
}
void FMC_SDRAM_WriteBuffer(unsigned char *pBuffer,unsigned int WriteAddr,unsigned int n)
{
	for(;n!=0;n--)
	{
		*(unsigned char*)(Bank5_SDRAM_ADDR+WriteAddr)=*pBuffer;
		WriteAddr++;
		pBuffer++;
	}
}
void FMC_SDRAM_ReadBuffer(unsigned char *pBuffer,unsigned int ReadAddr,unsigned int n)
{
	for(;n!=0;n--)
	{
		*pBuffer++=*(unsigned char*)(Bank5_SDRAM_ADDR+ReadAddr);
		ReadAddr++;
	}
}
void SDRAM_Initialization_Sequence()
{
	unsigned int temp=0;
  SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_CLK_ENABLE,1,0); 
  HAL_Delay(1);
	SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_PALL,1,0);   
  SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_AUTOREFRESH_MODE,8,0);
	temp=(unsigned int)SDRAM_MODEREG_BURST_LENGTH_1          |	
              SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |	
              SDRAM_MODEREG_CAS_LATENCY_2           |
              SDRAM_MODEREG_OPERATING_MODE_STANDARD |  
              SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;    
    SDRAM_Send_Cmd(0,FMC_SDRAM_CMD_LOAD_MODE,1,temp);  
 
	HAL_SDRAM_ProgramRefreshRate(&hsdram1,677);	
}	
/* USER CODE END 0 */

  /* USER CODE BEGIN 1 */
	unsigned char data[100];
	unsigned long long i = (2 * 1024 *1024);
  /* USER CODE END 1 */
  /* USER CODE BEGIN 2 */
	SDRAM_Initialization_Sequence();
	while(i--)
		FMC_SDRAM_WriteBuffer("1234567890abcdef",16*i,16);
	FMC_SDRAM_ReadBuffer(data,0,10);
  /* USER CODE END 2 */