功能说明:
1, 用了3个输入代表抢答按钮,如果想设置更过直接更改;
2, 初始时倒计时为10s;
3, 如果倒计时为10s没人抢答,按下复位键,重新开始抢答;
4, 在倒计时10s内有人抢答,则倒计时停止减一;
5, 序号显示的是第一个抢答的人对应的序号,其他人抢答无效;
6, 按下复位键,重新开始抢答。
代码如下:
`timescale 1ns/1ps
////////////////////////////////////////////////////////////////////////////////
// Company :
// Author : gong
// Create Date : 2012.8.24
// Design Name :
// Module Name : responder
// Project Name : responder
// Target Device: CycloneII EP2C8Q208C8
// Tool versions: QuartusII 9.0
// Description :
// Revision : V1.0
// Additional Comments :
////////////////////////////////////////////////////////////////////////////////
module responder (
clk,
rst_n,
// kaishi,
fuwei,
key1,
key2,
key3,
xuhao,
shijian
);
input clk;
input rst_n;
//input kaishi;
input fuwei;
input key1;
input key2;
input key3;
output [2:0] xuhao;
output [5:0] shijian;
wire [5:0] shijian;
reg [5:0] cnt;
assign shijian = cnt;
reg [2:0] xuhao;
reg [2:0] state;
parameter start=4'b0000, //开始
first=4'b0001, //第1位
second=4'b0010,//第2位
third=4'b0011, //第3位
fourth=4'b0100, //第4位
fifth=4'b0101, //第5位
sixth=4'b0110, //第6位
seventh=4'b0111, //第7位
eighth=4'b1000; //第8位
reg flg;
reg [2:0] haoma;
always @ (key1,key2,key3)
begin
if(key1)
haoma <= 1;
else if(key2)
haoma <= 2;
else if(key3)
haoma <= 3;
end
reg kaishi;
initial kaishi = 1;
wire bb;
assign bb = (key1 || key2 || key3)&& (!flg);
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) begin
state <= start;
xuhao <= 0;
cnt <= 10;
flg <= 0;
end
else
begin
case (state)
start:
if(kaishi) begin
cnt <= cnt - 1;
if(cnt==0)
state <= second; // xie wuwei de
else if(bb) begin
state <= first;
flg <= 1;
cnt <= cnt;
kaishi<= 0;
xuhao <= haoma;
end
else
state <= start;
end
first: begin
// xuhao <= haoma; 在这显示就出错误,不能锁存
state <= second;
end
second:
if(fuwei) begin
cnt <= 10;
state <= start;
flg <= 0;
kaishi<= 1;
xuhao <= 0;
end
else
state <= first;
endcase
end
end
endmodule
激励文件:
`timescale 1ns/1ps
module responder_tb;
reg clk;
reg rst_n;
reg fuwei;
reg key1;
reg key2;
reg key3;
wire [2:0] xuhao;
wire [5:0] shijian;
responder i1 (
.clk(clk),
.rst_n(rst_n),
.fuwei(fuwei),
.key1(key1),
.key2(key2),
.key3(key3),
.xuhao(xuhao),
.shijian(shijian)
);
parameter period = 10;
initial
begin
forever
#(period/2) clk = ~clk;
end
initial
begin
clk = 0;
rst_n = 0;
fuwei = 0;
key1 = 0;
key2 = 0;
key3 = 0;
#50 rst_n = 1;
#40 key1 = 1;
#10 key1 = 0;
key2 = 1; // 验证是不是锁存信号
#10 key2 = 0;
#200 fuwei = 1;
#10 fuwei = 0;
#30 key3 = 1;
#10 key3 = 0;
key2 = 1; // 验证是不是锁存信号
#10 key2 = 0;
#500
$stop;
end
endmodule
工程下载地址: http://download.csdn.net/detail/a14730497/4523327