记录verilog基础知识

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2018/12/20 22:56:56
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

`include “config_id.vh”

module test
(
input clk,
input rst,
input [19:0] data_in,
input vld,
input [7:0] res_in,
output reg com_result
);

reg [19:0]      res_data[0:7];
reg [2:0]       counter;
always @ (posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        counter <= 'b0;
    else
    begin
        if(vld == 1'b1)
        begin
            if(counter == 3'd7)
                counter <= 3'd0;
            else
                counter <= counter + 1;
        end 
    end 
end 

reg     [3:0]       i;
always @ (posedge clk or posedge rst)
begin
    if(rst == 1'b1)
    begin 
        for(i=0;i<8;i=i+1)
            res_data[i] = 'b0;
    end     
    else
    begin
        if(vld == 1'b1)
        begin
            res_data[counter] <= res_in;
        end 
    end 
end 

reg	  [19:0]        data_in_r;
always @ (posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        data_in_r <= 'b0;
    else
        data_in_r <= data_in;
end 

always @ (posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        com_result <= 1'b0;
    else    
    begin
        if(vld == 1'b1)
        begin
            if((COMP_DATA == data_in_r)  && (res_data[counter][7:1] == 'd50))
                com_result <= res_data[counter][0];
             else
                com_result <= CONFIG_ID[counter];
        end 
    end 
end 

endmodule

config_id.vh:

parameter COMP_DATA = 20’d113579;
parameter COMP_RES = 8’d100;
parameter CONFIG_ID[0:7] = {8’d1, 8’d1, 8’d31, 8’d44, 8’d12, 8’d88, 8’d93, 8’d12};

xdc:

set_property PACKAGE_PIN AD23 [get_ports clk]
set_property IOSTANDARD LVCMOS25 [get_ports clk]

create_clock -period 2 -name clk -waveform {0.000 1.00} [get_ports clk]

set_property LOC AB7 [ get_ports rst]
set_property IOSTANDARD LVCMOS15 [ get_ports rst]

set_property PACKAGE_PIN E19 [get_ports vld]
set_property IOSTANDARD LVCMOS25 [get_ports vld]

set_property PACKAGE_PIN C25 [get_ports com_result]
set_property IOSTANDARD LVCMOS25 [get_ports com_result]

set_property PACKAGE_PIN A23 [get_ports {data_in[0]}]

set_property PACKAGE_PIN A25 [get_ports {data_in[1]}]

set_property PACKAGE_PIN C24 [get_ports {data_in[2]}]

set_property PACKAGE_PIN A26 [get_ports {data_in[3]}]

set_property PACKAGE_PIN E24 [get_ports {data_in[4]}]

set_property PACKAGE_PIN E26 [get_ports {data_in[5]}]

set_property PACKAGE_PIN G24 [get_ports {data_in[6]}]

set_property PACKAGE_PIN H24 [get_ports {data_in[7]}]

set_property PACKAGE_PIN B27 [get_ports {data_in[8]}]

set_property PACKAGE_PIN A27 [get_ports {data_in[9]}]

set_property PACKAGE_PIN B23 [get_ports {data_in[10]}]

set_property PACKAGE_PIN D24 [get_ports {data_in[11]}]

set_property PACKAGE_PIN G28 [get_ports {data_in[12]}]

set_property PACKAGE_PIN B24 [get_ports {data_in[13]}]

set_property PACKAGE_PIN H25 [get_ports {data_in[14]}]

set_property PACKAGE_PIN E30 [get_ports {data_in[15]}]

set_property PACKAGE_PIN C30 [get_ports {data_in[16]}]

set_property PACKAGE_PIN B30 [get_ports {data_in[17]}]

set_property PACKAGE_PIN A30 [get_ports {data_in[18]}]

set_property PACKAGE_PIN F26 [get_ports {data_in[19]}]

set_property IOSTANDARD LVCMOS25 [get_ports data_in]

set_property PACKAGE_PIN AB8 [get_ports {res_in[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {res_in[0]}]
set_property PACKAGE_PIN AA8 [get_ports {res_in[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {res_in[1]}]
set_property PACKAGE_PIN AC9 [get_ports {res_in[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {res_in[2]}]
set_property PACKAGE_PIN AB9 [get_ports {res_in[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {res_in[3]}]
set_property PACKAGE_PIN L21 [get_ports {res_in[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {res_in[4]}]
set_property PACKAGE_PIN K21 [get_ports {res_in[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {res_in[5]}]
set_property PACKAGE_PIN AC26 [get_ports {res_in[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {res_in[6]}]
set_property PACKAGE_PIN AG28 [get_ports {res_in[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {res_in[7]}]