SystemVerilog 简单ALU模型

//definitions.sv

 1 `ifndef DEFS_DONE
 2 `define DEFS_DONE
 3 package definitions;
 4 
 5 parameter VERSION = "1.1";
 6 
 7 typedef enum bit [1:0]{ADD, SUB, MUL} opcodes_t;
 8 
 9 typedef struct{
10     logic [31:0] a, b;
11     opcodes_t opcode;
12 }instruction_t;
13 
14 function automatic [31:0] multiplier(input [31:0] a, b);
15     return a*b;
16 endfunction
17 
18 endpackage 
19 
20 import definitions::*;
21 
22 `endif

//ALU.sv

 1 `include "definitions.sv"
 2 module ALU(
 3 input     instruction_t     IW,
 4 input     logic             clock,
 5 output     logic [31:0]    result
 6 );
 7 
 8 always_comb begin
 9     case (IW.opcode)
10         ADD : result = IW.a + IW.b;
11         SUB : result = IW.a - IW.b;
12         MUL : result = multiplier(IW.a, IW.b);
13     endcase
14 end
15 endmodule 

//test.sv

 1 `include "definitions.sv"
 2 
 3 module test;
 4 
 5 instruction_t test_word;
 6 logic [31:0] alu_out;
 7 logic  clock = 0;
 8 
 9 ALU dut (.IW(test_word), .result(alu_out), .clock(clock));
10 
11 always #10 clock = ~ clock;
12 
13 initial begin
14 
15     @(negedge clock)
16     test_word.a = 5;
17     test_word.b = 7;
18     test_word.opcode = ADD;
19     @(negedge clock)
20     $display("alu_out = %d (expected 12)", alu_out);
21     $finish;
22 end
23 
24 endmodule