【VHDL】VHDL实现同步置数，异步复位的D触发器设计

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同步置数，异步复位的D触发器设计

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程序`

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY D IS
PORT (clk,R,S: IN STD_LOGIC;
		D: IN STD_LOGIC_vector(3 downto 0);
		Q: OUT STD_LOGIC_vector(3 downto 0));
END entity;

ARCHITECTURE one OF D IS
BEGIN
PROCESS(clk,R,S,D)
BEGIN
	IF R='1' THEN Q<=(others=>'0');
ELSIF clk'EVENT AND clk='1' THEN
	IF  S='1' THEN Q<="1111";
ELSE Q<=D;
	END IF;
END IF;
END PROCESS;
END;

仿真结果：

只为记录