VHDL设计触发器和锁存器

D触发器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dtrigger IS
	PORT(d,clk:IN STD_LOGIC;
		q,dq:OUT STD_LOGIC);
END dtrigger;
ARCHITECTURE dtrigger_behavior OF dtrigger IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN    --上升沿触发
			q<=d;
			dq<=NOT d;
		END IF;
	END PROCESS;
END dtrigger_behavior;

同步复位D触发器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dtrigger IS
	PORT(d,clk,rst:IN STD_LOGIC;
		q,dq:OUT STD_LOGIC);
END dtrigger;
ARCHITECTURE dtrigger_behavior OF dtrigger IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(rst='1')THEN		--同步复位
				q<='0';
				dq<='1';
			ELSE
				q<=d;
				dq<=NOT d;
			END IF;
		END IF;
	END PROCESS;
END dtrigger_behavior;

异步置位D触发器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dtrigger IS
	PORT(d,clk,rst:IN STD_LOGIC;
		q,dq:OUT STD_LOGIC);
END dtrigger;
ARCHITECTURE dtrigger_behavior OF dtrigger IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF(rst='1')THEN
			q<='0';
			dq<='1';
		ELSIF(clk'EVENT AND clk='1')THEN
			q<=d;
			dq<= NOT d;
		END IF;
	END PROCESS;
END dtrigger_behavior;

同步复位就是在时钟边沿来临的时候，复位信号才有作用。而异步复位则是复位信号一旦有效触发器就立即复位，而不是等待时钟边沿的来临。

D锁存器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dlock IS
	PORT(clk,d:IN STD_LOGIC;
		q:OUT STD_LOGIC);
END dlock;
ARCHITECTURE dlock_behavior OF dlock IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk='1')THEN
			q<=d;
		END IF;
	END PROCESS;
END dlock_behavior;