Proteus深入研究(四): SPICE模型
1. Overview................................................................................................................... 3
1.1. SPICE Simulation Program with Integrated Circuit Emphasis (SPICE)................... 3
1.2. SPICE Simulation Models and Netlists................................................................ 3
1.3. A Tradeoff Between Speed and Accuracy............................................................ 4
1.4. Using SPICE Simulation.................................................................................... 5
1.5. Learning More................................................................................................. 5
2. SPICE Simulation History............................................................................................ 6
2.1. Overview........................................................................................................ 6
2.2. SPICE Simulation History.................................................................................. 6
2.3. References...................................................................................................... 7
3. SPICE Simulation Models............................................................................................ 8
3.1. Overview........................................................................................................ 8
3.2. What is a SPICE Simulation Model?................................................................... 8
3.3. Model Makers.................................................................................................. 9
3.4. Where to look for SPICE Simulation models........................................................ 9
4. Basic SPICE Simulation Model Parameters................................................................... 12
4.1. Overview....................................................................................................... 12
4.2. Basic SPICE Simulation Devices...................................................................... 12
4.3. SPICE Model Syntax...................................................................................... 12
4.3.1. Resistors............................................................................................. 12
4.3.2. Semiconductor Resistors...................................................................... 13
4.3.3. Capacitors........................................................................................... 13
4.3.4. Semiconductor Capacitors.................................................................... 13
4.3.5. Inductors............................................................................................ 13
4.3.6. Coupled (Mutual) Inductors.................................................................. 14
4.3.7. Switches............................................................................................. 14
4.3.8. Voltage Sources................................................................................... 14
4.3.9. Current Sources................................................................................... 15
4.3.10. Linear Voltage-Controlled Current Sources.............................................. 15
4.3.11. Linear Voltage-Controlled Voltage Sources............................................... 15
4.3.12. Linear Current-Controlled Current Sources............................................. 16
4.3.13. Linear Current-Controlled Voltage Sources.............................................. 16
4.3.14. Non-linear Dependent Sources............................................................... 16
4.3.15. Lossless Transmission Lines................................................................. 17
4.3.16. Uniform Distributed RC Lines (lossy)..................................................... 17
4.3.17. Junction Diodes................................................................................... 17
4.3.18. Bipolar Junction Transistors (BJT)......................................................... 17
4.3.19. Junction Field-Effect Transistors (JFET)................................................ 18
4.3.20. MOSFETs........................................................................................... 18
4.3.21. MESFETs........................................................................................... 18
5. Advanced SPICE Simulation Model Parameters............................................................ 20
5.1. Overview....................................................................................................... 20
5.2. Advanced Model Parameters............................................................................ 20
6. SPICE Simulation Options.......................................................................................... 31
6.1. Overview....................................................................................................... 31
6.2. What are SPICE Simulation Options?................................................................ 31
6.3. A Tradeoff Between Speed and Accuracy.......................................................... 31
6.4. Changing SPICE Simulation Options................................................................. 32
6.5. A Listing of SPICE Simulation Options.............................................................. 33
Option................................................................................................ 33
Effect................................................................................................. 33
6.6. SPICE2 Emulation Mode....................................................................... 34
Option................................................................................................ 34
Effect................................................................................................. 34
7. SPICE Simulation and Control Statements.................................................................... 35
7.1. Overview............................................................................................ 35
7.2. Available Analyses and Control Statements.............................................. 35
7.3. SPICE Analyses and Control Statement Syntax........................................ 36
7.3.1. Operating Point Analysis....................................................................... 36
7.3.2. DC Transfer Function.......................................................................... 36
7.3.3. Small-Signal AC Analysis....................................................................... 37
7.3.4. Distortion Analysis............................................................................... 37
7.3.5. Noise Analysis..................................................................................... 38
7.3.6. Pole-Zero Analysis................................................................................ 38
7.3.7. Sensitivity Analysis (DC or Small Signal AC)........................................... 39
7.3.8. Transfer Function Analysis.................................................................... 39
7.3.9. Transient Analysis................................................................................ 39
7.3.10. PRINT Output..................................................................................... 40
7.3.11. PLOT Output...................................................................................... 40
7.3.12. SAVE Output....................................................................................... 40
7.3.13. Fourier Analysis of Transient Analysis Output.......................................... 41
7.3.14. Specify Initial Node Voltage Guesses...................................................... 41
7.3.15. Set Initial Conditions............................................................................. 41
8. SPICE Source Types and Parameters.......................................................................... 43
8.1. Overview............................................................................................ 43
8.2. SPICE Simulation Sources.................................................................... 43
8.3. Using SPICE Simulation Sources........................................................... 44
8.3.1. Pulse.................................................................................................. 44
8.3.2. Sinusoid.............................................................................................. 44
8.3.3. Exponential.......................................................................................... 44
8.3.4. Piece-Wise Linear................................................................................. 45
8.3.5. Single Frequency FM........................................................................... 45
1. Overview
The National Instruments SPICE Simulation Fundamentals series is your free resource on the internet for learning about circuit simulation. The series is a set of tutorials and information on SPICE simulation, OrCAD pSPICE compatibility, SPICE modeling, and other concepts in circuit simulation.
For more information, see the SPICE Simulation Fundamentals main page.
The series is divided among a number of in-depth detailed articles that will give you HOW TO information on the important concepts and details of SPICE simulation.
Circuit simulation is an important part of any design process. By simulating your circuits, you can detect errors early in the process, and avoid costly and time consuming prototype reworking. You can also easily swap components to evaluate designs with varying bills of materials (BOMs).
1.1. SPICE Simulation Program with Integrated Circuit Emphasis (SPICE)
SPICE is a computer simulation and modeling program used by engineers to mathematically predict the behavior of electronics circuits. Developed at the University of California at Berkeley, SPICE can be used to simulate circuits of almost all complexities. However, SPICE is generally used to predict the behavior of low to mid frequency (DC to around 100MHz) circuits.
1.2. SPICE Simulation Models and Netlists
SPICE has the ability to simulate components ranging from the most basic passive elements such as resistors and capacitors to sophisticated semiconductor devices such as MESFETs and MOSFETs. Using these intrinsic components as the basic building blocks for larger models, designers and chip manufacturers have been able to define a truly vast and diverse number of SPICE models. Most commercially available simulators include more than 15,000 different components.
The quality of SPICE models can vary, and not all SPICE models are applicable to every application. It is important to consider this when using the models supplied with a SPICE simulation package. Using a SPICE model inappropriately can lead to inaccurate results, or even generate an error in some circumstances. One of the most common errors made by even seasoned engineers is confusing a SPICE model with a PSPICE model. PSPICE is a commercially available program that uses proprietary languages to define components and models.
A circuit must be presented to SPICE in the form of a netlist. The netlist is a text description of all circuit elements such as transistors and capacitors, and their corresponding connections. Modern schematic capture and simulation tools such as Multisim allow users to draw circuit schematics in a user-friendly environment, and automatically translate the circuit diagrams into netlists. Consider as an example the simple voltage divider circuit below. We include both netlist and corresponding circuit schematic.
| Voltage Divider Netlist |
Voltage Divider Schematic |
| * Any text after the asterisk '*' is ignored by SPICE
|
|
1.3. A Tradeoff Between Speed and Accuracy
Although the SPICE models used in a SPICE simulation can greatly affect the accuracy of the results, simulation settings also contribute to varying degrees of accuracy. SPICE simulation options generally allow the user to gain more accuracy in the results at the cost of the speed of the simulation.
To understand the tradeoff between speed and accuracy in SPICE simulation one must consider a number of factors. SPICE simulation was created over 30 years go and around that time a typical computer had less power than the average microwave oven did thirty years later. Computing power was very expensive. The simulation of a circuit to the highest degree of accuracy could have taken longer and cost more money than building the actual circuit to see the results. Also, consider that the broad purpose of circuit simulation is to augment basic hand calculations and predict general circuit behavior. With these considerations in mind, the designers of SPICE created a program that could produce reasonably accurate results in a cost-effective manner. They also included many options to allow engineers to customize the accuracy of a simulation.
As computing power has increased exponentially over the years, so have the complexity of circuit designs being simulated. Speed and accuracy are still important factors to consider when simulating circuits.
1.4. Using SPICE Simulation
SPICE Simulation by itself can be used as a command line or text-based simulation tool. However, to effectively manage large and complex designs that span from simulation through to PCB layout and routing, several commercial software tools have been built around SPICE and XSPICE including Multisim. Included in Multisim is a graphical user interface to allow quick and efficient schematic capture, and interactive simulation.
1.5. Learning More
To learn more about SPICE simulation, please see the SPICE Simulation Fundamentals home page.
2. SPICE Simulation History
2.1. Overview
The National Instruments SPICE Simulation Fundamentals series is your free resource on the internet for learning about circuit simulation. The series is a set of tutorials and information on SPICE simulation, OrCAD pSPICE compatibility, SPICE modeling, and other concepts in circuit simulation.
For more information, see the SPICE Simulation Fundamentals main page.
The series is divided among a number of in-depth detailed articles that will give you HOWTO information on the important concepts and details of SPICE simulation.
Circuit simulation is an important part of any design process. By simulating your circuits, you can detect errors early in the process, and avoid costly and time consuming prototype reworking. You can also easily swap components to evaluate designs with varying bills of materials (BOMs).
SPICE simulation has been used for over thirty years to accurately predict the behavior of electronic circuits. Over the years the many revisions of SPICE have seen improvements in both accuracy and speed. In addition to these improvements, additions to the language have allowed simulation and modeling of more complex integrated circuits including MOSFETs.
2.2. SPICE Simulation History
Simulation Program with Integrated Circuit Emphasis, or SPICE, has been used for over thirty years. The original implementation of SPICE was developed at the University of California Berkeley campus in the late 1960s. SPICE was developed largely as a derivative of CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation) also developed by UC Berkeley.
The first widely used version of SPICE was announced in Waterloo, Canada in 1973. Shortly thereafter SPICE was adopted by nearly all major engineering institutions throughout North America. SPICE has evolved into the academic and industry standard for analog and mixed-mode circuit simulation.
Over the years additional simulation algorithms, component models, bug fixes, and capabilities were added to the program. Even today SPICE is still the most widely used circuit simulator in the world and as of 2006 the latest version is SPICE 3F5.
XSPICE was developed at Georgia Tech as an extension to the SPICE language. XSPICE allows behavioral modeling of components which can drastically improve the speeds of mixed-mode and digital simulations. Multisim from National Instruments is based on SPICE 3F5 and XSPICE and provides additional convergence and speed improvements to complement these powerful simulation languages.
2.3. References
The SPICE Book, Andrei Vladimirescu, © 1994 John Wiley & Sons
The Life of SPICE, Laurence W. Nagel, © 1996
3. SPICE Simulation Models
3.1. Overview
The National Instruments SPICE Simulation Fundamentals series is your free resource on the internet for learning about circuit simulation. The series is a set of tutorials and information on SPICE simulation, OrCAD pSPICE compatibility, SPICE modeling, and other concepts in circuit simulation.
For more information, see the SPICE Simulation Fundamentals main page.
The series is divided among a number of in-depth detailed articles that will give you HOWTO information on the important concepts and details of SPICE simulation.
Circuit simulation is an important part of any design process. By simulating your circuits, you can detect errors early in the process, and avoid costly and time consuming prototype reworking. You can also easily swap components to evaluate designs with varying bills of materials (BOMs).
An important key to performing accurate and successful SPICE simulation is to use high quality SPICE models. While most circuit simulation packages such as Multisim come with thousands of components and SPICE simulation models, frequently designers need to use a part that does not exist in the available database. When these situations arise, the software tool will typically have a way of adding custom components and models to the database. Multisim for example has a detailed component creation wizard that will guide designers through the process of defining custom parts for simulation and PCB layout (See Creating Custom Components in Multisim).
3.2. What is a SPICE Simulation Model?
A SPICE model is a text-description of a circuit component used by the SPICE Simulator to mathematically predict the behavior of that part under varying conditions. SPICE models range from the simplest one line descriptions of a passive component such as a resistor, to extremely complex sub-circuits that can be hundreds of lines long.
SPICE models should not be confused with pSPICE models. pSPICE is a proprietary circuit simulator provided by OrCAD. While some pSPICE models are compatible with SPICE, there is no guarantee. SPICE is the most widely used circuit simulator, and is an open standard.
3.3. Model Makers
Some SPICE simulation programs such as Multisim include model makers to automatically generate SPICE models for various components. Multisim version 10.1 has 24 SPICE Model makers.
3.4. Where to look for SPICE Simulation models
The best place to look for SPICE models is to browse the vendor or manufacturer’s website. Listed below are some of the most popular chip vendors that supply SPICE models on their website.
| Vendor |
Description |
| Analog Devices |
Amplifiers and Comparators, Analog to Digital Converters, Digital to Analog Converters, Embedded Processing & DSP, MEMS and Sensors, RF/IF Components, Switches/Multiplexers, Analog Microcontrollers, Interface, Power and Thermal Management |
| Analog and RF Models |
Analog and RF Models |
| Apex Microtechnology |
Linear Amplifiers, PWM Amplifiers |
| Christophe Basso |
Switch-mode power supplies |
| Coilcraft, Inc. |
Power Magnetics, RF Inductors, EMI / RFI Filters, Broadband Magnetics |
| Directed Energy |
Diodes, Switch-mode MOSFETs, HF / VHF Linear MOSFETs, MOSFET Driver ICs |
| Duncan Amps |
Amplifiers, Vacuum tubes |
| Fairchild Semiconductors |
Amplifiers & Comparators, Diodes & Rectifiers, Interfaces, Digital Logic Devices, Signal Conversion, Voltage to Frequency Converters, Microcontroller, Optoelectronics, Switches, Power Controllers, Power Drivers, Transistors, Filters, Voltage Regulators |
| Infineon Technologies AG |
Fiber Optics, Microcontrollers, Power Semiconductors, Small Signal Discretes |
| International Rectifier |
HEXFET Power MOSFETs, Diodes, Bridges, Thyristors, Relays, High Voltage ICs, Intelligent Power Modules, Intelligent Power Switch, HiRel Power MOSFETs, HiRel High Voltage Gate Drivers |
| Kemet Home Page |
Surface-mount capacitors in aluminum, ceramic and tantalum and leaded capacitors in ceramic and tantalum |
| Linear Technology |
Signal Conditioning, Data Conversion, Power Management, Interfacing, High Freuqency & Optical |
| Maxim |
Amplifiers and Comparators, Analog Switches and Multiplexers, Clocks, Counters, Delay Lines, Oscillators, RTCs, Data Converters, Sample-and-Holds, Digital Potentiometers, Fiber and Communications, Filters (Analog), High-Frequency ASICs, Hot-Swap and Power Switching, Interface and Interconnect, Memories: Volatile, NV, Multi-Function, Thermal Management, Sensors, Sensor Conditioners, Voltage References, Wireless, RF, and Cable |
| National Semiconductor |
Amplifiers,Power Management, Temp Sensors, Interface, LVDS, Ethernet, USB Technologies, Micro SMD |
| ON Semiconductor |
Power Management, Amplifiers, Comparators, Analog Switches, Thyristors, Diodes, Rectifiers, Bipolar Transistors, FETs, Standard Logic, Differential Logic, |
| Philips |
Analog/Linear, Audio, Automotive, Connectivity, Data/Media/Video processing, Discretes, Displays, Interface and control, Logic, Microcontrollers, Power and power management, RF, Sensors |
| Polyfet |
Polyfet transistors |
| Protek |
Transient Voltage Suppression |
| SMPS Power Supplies |
Switch-mode power supply simulation |
| SMPS Technology |
Switch-mode power supply design |
| Supertex |
Mixed signal semiconductor, High-voltage interface products |
| STMicroelectronics |
Amplifiers & Linear,Analog & Mixed Signal ICs, Diodes, EMI Filtering & Conditioning, Logic, Signal Switch, Memories, Microcontrollers, Power Management, Protection Devices, Sensors, Smartcard ICs, Thyristors & AC Switches, Transistors |
| Texas Instruments |
Buffers, Drivers and Transceivers, Flip-Flops, Latches and Registers, Gates, Counters, Decoders/Encoders/Multiplexers, Digital Comparators |
| Tyco Electronics (formerly Amp) |
Electromechanical components, passive components, power sources, RF & Microwave products |
| Vishay |
Manufacturer of analog switches, capacitors, diodes, inductors, integrated modules, power ICs, LEDs, power MOSFETs, resistors and thermistors. |
| Zetex |
DC-DC boost controllers, Voltage references, Current monitors, Motor control, Acoustar™ audio solutions, Linear regulators |
4. Basic SPICE Simulation Model Parameters
4.1. Overview
The National Instrument SPICE Simulation Fundamentals series is your free resource on the internet for learning about circuit simulation. The series is a set of tutorials and information on SPICE simulation, OrCAD pSPICE compatibility, SPICE modeling, and other concepts in circuit simulation.
For more information, see the SPICE Simulation Fundamentals main page.
The series is divided among a number of in-depth detailed articles that will give you HOWTO information on the important concepts and details of SPICE simulation.
Circuit simulation is an important part of any design process. By simulating your circuits, you can detect errors early in the process, and avoid costly and time consuming prototype reworking. You can also easily swap components to evaluate designs with varying bills of materials (BOMs).
4.2. Basic SPICE Simulation Devices
SPICE includes several different types of electrical components that can be simulated. These range from simple resistors, to sophisticated MESFETs. The table below lists these components and their SPICE syntax.
4.3. SPICE Model Syntax
Parameters in angular parentheses <> are optional. If left unspecified, the default SPICE parameter values will be used.
4.3.1. Resistors
| Syntax |
Rname n1 n2 value |
| Example |
Rin 2 0 100 |
| Notes |
n1 and n2 are the two element nodes. Value is the resistance (in ohms) and may be positive or negative but not zero. |
4.3.2. Semiconductor Resistors
| Syntax |
Rname n1 n2 |
| Example |
Rload 3 7 RMODEL L=10u W=1u |
| Notes |
This is the more general form of the resistor and allows the modeling of temperature effects and for the calculation of the actual resistance value from strictly geometric information and the specifications of the process. |
4.3.3. Capacitors
| Syntax |
Cname n+ n- value |
| Example |
Cout 13 0 1UF IC=3V |
| Notes |
n+ and n- are the positive and negative element nodes, respectively. Value is the capacitance in Farads. The (optional) initial condition is the initial (time-zero) value of capacitor voltage (in Volts). |
4.3.4. Semiconductor Capacitors
| Syntax |
Cname n1 n2 |
| Example |
Cfilter 3 7 CMODEL L=10u W=1u |
| Notes |
This is the more general form of the Capacitor and allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. |
4.3.5. Inductors
| Syntax |
Lname n+ n- value |
| Example |
LSHUNT 23 51 10U IC=15.7MA |
| Notes |
n+ and n- are the positive and negative element nodes, respectively. Value is the inductance in Henries. The (optional) initial condition is the initial (time-zero) value of inductor current (in Amps) that flows from n+, through the inductor, to n-. |
4.3.6. Coupled (Mutual) Inductors
| Syntax |
Kname Lname1 Lname2 value |
| Example |
Kin L1 L2 0.87 |
| Notes |
Lname1 and Lname2 are the names of the two coupled inductors, and VALUE is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. |
4.3.7. Switches
| Syntax |
Sname n+ n- nc+ nc- Mname |
| Examples |
Switch1 1 2 10 0 smodel1 |
| Notes |
Nodes n+ and n- are the nodes between which the switch terminals are connected. The model name is mandatory while the initial conditions are optional. For the voltage controlled switch, nodes nc+ and nc- are the positive and negative controlling nodes respectively. For the current controlled switch, the controlling current is that through the specified voltage source. The direction of positive controlling current flow is from the positive node, through the source, to the negative node. |
4.3.8. Voltage Sources
| Syntax |
Vname n+ n- |
| Examples |
VCC 10 0 DC 6 |
| Notes |
n+ and n- are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value forces current to flow out of the n+ node, through the source, and into the n- node. Voltage sources, in addition to being used for circuit excitation, are the 'ammeters' for SPICE, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They of course have no effect on circuit operation since they represent short-circuits. DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC. |
4.3.9. Current Sources
| Syntax |
Iname n+ n- < |
| Examples |
Igain 12 15 DC 1 |
| Notes |
ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If ACPHASE is omitted, a value of zero is assumed. If the source is not an ac small-signal input, the keyword AC and the ac values are omitted. DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion inputs at the frequencies F1 and F2 respectively (see the description of the .DISTO control line). The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively. |
4.3.10. Linear Voltage-Controlled Current Sources
| Syntax |
Gname n+ n- nc+ nc- value |
| Example |
G1 2 0 5 0 0.1MMHO |
| Notes |
n+ and n- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. nc+ and nc- are the positive and negative controlling nodes, respectively. VALUE is the transconductance (in mhos). |
4.3.11. Linear Voltage-Controlled Voltage Sources
| Syntax |
Ename n+ n- nc+ nc- value |
| Example |
E1 2 3 14 1 2.0 |
| Notes |
n+ is the positive node, and n- is the negative node. nc+ and nc- are the positive and negative controlling nodes, respectively. Value is the voltage gain. |
4.3.12. Linear Current-Controlled Current Sources
| Syntax |
Fname n+ n- Vname value |
| Example |
F1 13 5 Vsen 5 |
| Notes |
n+ andn- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. Vname is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of Vname. Value is the current gain. |
4.3.13. Linear Current-Controlled Voltage Sources
| Syntax |
Hname n+ n- Vname value |
| Example |
Hx1 5 17 Vz 0.5K |
| Notes |
n+ and n- are the positive and negative nodes, respectively. Vnameis the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of Vname. Value is the transresistance (in ohms). |
4.3.14. Non-linear Dependent Sources
| Syntax |
Bname n+ n- |
| Example |
B1 0 1 I=cos(v(1))+sin(v(2)) |
| Notes |
n+ is the positive node, and n- is the negative node. The values of the V and I parameters determine the voltages and currents across and through the device, respectively. If I is given then the device is a current source, and if V is given the device is a voltage source. One and only one of these parameters must be given. The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point. |
4.3.15. Lossless Transmission Lines
| Syntax |
Oname n1 n2 n3 n4 Mname |
| Example |
O23 1 0 2 0 LOSSYMOD |
| Notes |
This is a two-port convolution model for single-conductor lossy transmission lines. n1 and n2 are the nodes at port 1; n3 and n4 are the nodes at port 2. Note that a lossy transmission line with zero loss may be more accurate than than the lossless transmission line due to implementation details. |
4.3.16. Uniform Distributed RC Lines (lossy)
| Syntax |
Uname n1 n2 n3 Mname L=LEN |
| Example |
U1 1 2 0 URCMOD L=50U |
| Notes |
n1 and n2 are the two element nodes the RC line connects, while n3 is the node to which the capacitances are connected. Mname is the model name, LEN is the length of the RC line in meters. Lumps, if specified, is the number of lumped segments to use in modeling the RC line (see the model description for the action taken if this parameter is omitted). |
4.3.17. Junction Diodes
| Syntax |
Dname n+ n- Mname |
| Example |
Dfwd 3 7 DMOD 3.0 IC=0.2 |
| Notes |
n+ and n- are the positive and negative nodes, respectively. Mname is the model name, Area is the area factor, and OFF indicates an (optional) starting condition on the device for dc analysis. |
4.3.18. Bipolar Junction Transistors (BJT)
| Syntax |
Qname nC nB nE |
| Example |
Q23 10 24 13 QMOD IC=0.6, 5.0 |
| Notes |
nC, nB, andnE are the collector, base, and emitter nodes, respectively. nS is the (optional) substrate node. If unspecified, ground is used. Mname is the model name, Area is the area factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. |
4.3.19. Junction Field-Effect Transistors (JFET)
| Syntax |
Jname nD nG nS Mname |
| Example |
J1 7 2 3 JM1 OFF |
| Notes |
nD, nG, and nS are the drain, gate, and source nodes, respectively. Mname is the model name, Area is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. |
4.3.20. MOSFETs
| Syntax |
Mname ND NG NS NB MNAME |
| Example |
M31 2 17 6 10 Mname L=5U W=2U |
| Notes |
nD, nG, nS, and nB are the drain, gate, source, and bulk (substrate) nodes, respectively. Mname is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in 2 meters . Note that the suffix U specifies microns (1e-6 m) 2 and P sq-microns (1e-12 m ). If any of L, W, AD, or AS are not specified, default values are used. |
4.3.21. MESFETs
| Syntax |
Zname nD nG nS Mname |
| Example |
Z1 7 2 3 ZM1 OFF |
| Notes |
nD, nG, andnS are the drain, gate, and source nodes, respectively. Mname is the model name, Area is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. |
| Type |
Abbr |
| Resistors |
R |
| Semiconductor Resistors |
R |
| Capacitors |
C |
| Semiconductor Capacitors |
C |
| Inductors |
L |
| Coupled (Mutual) Inductors |
K |
| Switches |
S |
| Voltage Sources |
V |
| Current Sources |
I |
| Linear Voltage-Controlled Current Sources |
G |
| Linear Voltage-Controlled Voltage Sources |
E |
| Linear Current-Controlled Current Sources |
F |
| Linear Current-Controlled Voltage Sources |
H |
| Non-linear Dependent Sources |
B |
| Lossless Transmission Lines |
O |
| Uniform Distributed RC Lines (lossy) |
U |
| Junction Diodes |
D |
| Bipolar Junction Transistors (BJT) |
Q |
| Junction Field-Effect Transistors (JFET) |
J |
| MOSFETs |
M |
| MESFETs |
Z |
5. Advanced SPICE Simulation Model Parameters
5.1. Overview
The National Instruments SPICE Simulation Fundamentals series is your free resource on the internet for learning about circuit simulation. The series is a set of tutorials and information on SPICE simulation, OrCAD pSPICE compatibility, SPICE modeling, and other concepts in circuit simulation.
For more information, see the SPICE Simulation Fundamentals main page.
The series is divided among a number of in-depth detailed articles that will give you HOWTO information on the important concepts and details of SPICE simulation.
Circuit simulation is an important part of any design process. By simulating your circuits, you can detect errors early in the process, and avoid costly and time consuming prototype reworking. You can also easily swap components to evaluate designs with varying bills of materials (BOMs).
5.2. Advanced Model Parameters
The SPICE language can model many sophisticated real world effects such as the result of temperature variations on a component.
The attached document lists the detailed model parameters for all the native SPICE models.
| Model Name |
No |
Name |
Parameter |
Units |
Default |
Example |
| Semiconductor Resistor Model ( R ) |
1 |
TC1 |
first order temperature coeff. |
Ohm/°C |
0.0 |
|
|
|
2 |
TC2 |
second order temperature coeff. |
Ohm/C² |
0.0 |
- |
|
|
3 |
RSH |
sheet resistance |
Ohm/q |
- |
50 |
|
|
4 |
DEFW |
default width |
meters |
1.e-6 |
2.e-6 |
|
|
5 |
NARROW |
narrowing due to side etching |
meters |
0.0 |
1.e-7 |
|
|
6 |
TNOM |
parameter measurement temperature |
°C |
27 |
50 |
|
|
|
|
|
|
|
|
| Semiconductor Capacitor Model ( C ) |
1 |
CJ |
junction bottom capacitance |
F/meters2 |
- |
5.e-5 |
|
|
2 |
CJSW |
junction sidewall capacitance |
F/meters |
- |
2.e-11 |
|
|
3 |
DEFW |
default device width |
meters |
1.e-6 |
2.e-6 |
|
|
4 |
NARROW |
narrowing due to side etching |
meters |
0.0 |
1.e-7 |
|
|
|
|
|
|
|
|
| Switch Model ( SW/CSW ) |
1 |
VT |
threshold voltage |
Volts |
0.0 |
S |
|
|
2 |
IT |
threshold current |
Amps |
0.0 |
W |
|
|
3 |
VH |
hysteresis voltage |
Volts |
0.0 |
S |
|
|
4 |
IH |
hysteresis current |
Amps |
0.0 |
W |
|
|
5 |
RON |
on resistance |
Ohms |
1.0 |
both |
|
|
6 |
ROFF |
off resistance |
Ohms |
1/GMIN* |
both |
|
|
|
|
|
|
|
|
| Lossy Transmission Line Model (lTRA) |
1 |
R |
resistance/length |
|
0.0 |
0.2 |
|
|
2 |
L |
inductance/length |
henrys/unit |
0.0 |
9.13e-9 |
|
|
3 |
G |
conductance/length |
mhos/unit |
0.0 |
0.0 |
|
|
4 |
C |
capacitance/length |
farads/unit |
0.0 |
3.65e-12 |
|
|
5 |
LEN |
lenght of line |
|
no default |
1.0 |
|
|
6 |
REL |
breakpoint control |
arbitrary unit |
1 |
0.5 |
|
|
7 |
ABS |
breakpoint control |
|
1 |
5 |
|
|
8 |
NOSTEPLIMIT |
don't limit timestep to less than line delay |
flag |
not set |
set |
|
|
9 |
NOCONTROL |
don't do complex timestep control |
flag |
not set |
set |
|
|
10 |
LININTERP |
use lineair interpolation |
flag |
not set |
set |
|
|
11 |
MIXEDINTERP |
use lineair when quadratic seems bad |
|
not set |
set |
|
|
12 |
COMPACTREL |
special reltol for history compaction |
flag |
RELTOL |
1.0e-3 |
|
|
13 |
COMPACTABS |
special abstol for history compaction |
|
ABSTOL |
1.0e-9 |
|
|
14 |
TRUNCNR |
use Newton-Raphson method for timestep control |
flag |
not set |
set |
|
|
15 |
TRUNCDONTCUT |
don't limit timestep to keep impulse-response errors low |
flag |
not set |
set |
|
|
|
|
|
|
|
|
| Uniform Distributed RC Model (URC) |
1 |
K |
Propagation Constant |
- |
2.0 |
1.2 |
|
|
2 |
FMAX |
Maximum Frequency of interest |
Hz |
1.0G |
6.5Meg |
|
|
3 |
RPERL |
Resistance per unit length |
Ohms |
1000 |
10 |
|
|
4 |
CPERL |
Capacitance per unit length |
F/m |
1.0e-15 |
1pF |
|
|
5 |
ISPERL |
Saturation Current per unit length |
A/m |
0 |
- |
|
|
6 |
RSPERL |
Diode Resistance per unit length |
Ohms |
0 |
- |
|
|
|
|
|
|
|
|
| Diode Model ( D ) |
1 |
IS |
saturation current |
A |
1.0e-14 |
1.0e-14 |
|
|
2 |
RS |
ohmic resistance |
Ohms |
0 |
10 |
|
|
3 |
N |
emission coefficient |
- |
1 |
1.0 |
|
|
4 |
TT |
transit-time |
sec |
0 |
0.1ns |
|
|
5 |
CJO |
zero-bias junction capacitance |
F |
0 |
2pF |
|
|
6 |
VJ |
junction potential |
V |
1 |
0.6 |
|
|
7 |
M |
grading coefficient |
- |
0.5 |
0.5 |
|
|
8 |
EG |
activation energy |
eV |
1.11 |
1.11 Si |
|
|
0.69 Sbd |
|||||
|
|
0.67Ge |
|||||
|
|
9 |
XTI |
saturation-current temp. exp |
- |
3.0 |
3.0jn |
|
|
2.0Sbd |
|||||
|
|
10 |
KF |
flicker noise coefficient |
- |
0 |
|
|
|
11 |
AF |
flicker noise exponent |
- |
1 |
|
|
|
12 |
FC |
coefficient for forward-bais depletion capacitance formula |
- |
0.5 |
|
|
|
13 |
BV |
reverse breakdown voltage |
V |
infinite |
40.0 |
|
|
14 |
IBV |
current at breakdown voltage |
A |
1.0e-3 |
|
|
|
15 |
TNOM |
parameter measurement temperature |
°C |
27 |
50 |
|
|
|
|
|
|
|
|
| BJT Models (NPN/PNP) |
1 |
IS |
transport saturation current |
A |
1.0e-16 |
1.0e-15 |
|
|
2 |
BF |
ideal maximum forward beta |
- |
100 |
100 |
|
|
3 |
NF |
forward current emission coefficient |
- |
1.0 |
1 |
|
|
4 |
VAF |
forward Early voltage |
V |
infinite |
200 |
|
|
5 |
IKF |
corner for forward beta high current roll-off |
A |
infinite |
0.01 |
|
|
6 |
ISE |
B-E leakage saturation current |
A |
0 |
1.0e-13 |
|
|
7 |
NE |
B-E leakage emission coefficient |
- |
1.5 |
2 |
|
|
8 |
BR |
ideal maximum reverse beta |
- |
1 |
0.1 |
|
|
9 |
NR |
reverse current emission coefficient |
- |
1 |
1 |
|
|
10 |
VAR |
reverse Early voltage |
V |
infinite |
200 |
|
|
11 |
IKR |
corner for reverse beta high current roll-off |
A |
infinite |
0.01 |
|
|
12 |
ISC |
leakage saturation current |
A |
0 |
|
|
|
13 |
NC |
leakage emission coefficient |
- |
2 |
1.5 |
|
|
14 |
RB |
zero bias base resistance |
Ohms |
0 |
100 |
|
|
15 |
IRB |
current where base resistance falls halfway to its min value |
A |
infinte |
0.1 |
|
|
16 |
RBM |
minimum base resistance at high currents |
Ohms |
RB |
10 |
|
|
17 |
RE |
emitter resistance |
Ohms |
0 |
1 |
|
|
18 |
RC |
collector resistance |
Ohms |
0 |
10 |
|
|
19 |
CJE |
B-E zero-bias depletion capacitance |
F |
0 |
2pF |
|
|
20 |
VJE |
B-E built-in potential |
V |
0.75 |
0.6 |
|
|
21 |
MJE |
B-E junction exponential factor |
- |
0.33 |
0.33 |
|
|
22 |
TF |
ideal forward transit time |
sec |
0 |
0.1ns |
|
|
23 |
XTF |
coefficient for bias dependence of TF |
- |
0 |
|
|
|
24 |
VTF |
voltage describing VBC |
V |
infinite |
|
|
|
dependence of TF |
|||||
|
|
25 |
ITF |
high-current parameter |
A |
0 |
|
|
|
for effect on TF |
|||||
|
|
26 |
PTF |
excess phase at freq=1.0/(TF*2PI) Hz |
deg |
0 |
|
|
|
27 |
CJC |
B-C zero-bias depletion capacitance |
F |
0 |
2pF |
|
|
28 |
VJC |
B-C built-in potential |
V |
0.75 |
0.5 |
|
|
29 |
MJC |
B-C junction exponential factor |
- |
0.33 |
0.5 |
|
|
30 |
XCJC |
fraction of B-C depletion capacitance |
- |
1 |
|
|
|
connected to internal base node |
|||||
|
|
31 |
TR |
ideal reverse transit time |
sec |
0 |
10ns |
|
|
32 |
CJS |
zero-bias collector-substrate capacitance |
F |
0 |
2pF |
|
|
33 |
VJS |
substrate junction built-in potential |
V |
0.75 |
|
|
|
34 |
MJS |
substrate junction exponential factor |
- |
0 |
0.5 |
|
|
35 |
XTB |
forward and reverse beta |
- |
0 |
|
|
|
temperature exponent |
|||||
|
|
36 |
EG |
energy gap for temperature |
eV |
1.11 |
|
|
|
effect on IS |
|||||
|
|
37 |
XTI |
temperature exponent for effect on IS |
- |
3 |
|
|
|
38 |
KF |
flicker-noise coefficient |
- |
0 |
|
|
|
39 |
AF |
flicker-noise exponent |
- |
1 |
|
|
|
40 |
FC |
coefficient for forward-bias |
- |
0.5 |
|
|
|
depletion capacitance formula |
|||||
|
|
41 |
TNOM |
Parameter measurement temperature |
°C |
27 |
50 |
|
|
|
|
|
|
|
|
| JFET Models (NJF/PJF) |
1 |
VTO |
threshold voltage (VT0) |
V |
-2.0 |
-2.0 |
|
|
2 |
BETA |
transconductance parameter (beta) |
A/V2 |
1.0e-4 |
1.0e-3 |
|
|
3 |
LAMBDA |
channel-length modulation parameter (A) |
1/V |
0 |
1.0e-4 |
|
|
4 |
RD |
drain ohmic resistance |
Ohms |
0 |
100 |
|
|
5 |
RS |
source ohmic resistance |
Ohms |
0 |
100 |
|
|
6 |
CGS |
zero-bias G-S junction capacitance (Cgs) |
F |
0 |
5pF |
|
|
7 |
CGD |
zero-bias G-D junction capacitance (Cgs) |
F |
0 |
1pF |
|
|
8 |
PB |
gate junction potential |
V |
1 |
0.6 |
|
|
9 |
IS |
gate junction saturation current (IS) |
A |
1.0e-14 |
1.0e-14 |
|
|
10 |
B |
doping tail parameter |
- |
1 |
1.1 |
|
|
11 |
KF |
flicker noise coefficient |
- |
0 |
|
|
|
12 |
AF |
flicker noise exponent |
- |
1 |
|
|
|
13 |
FC |
coefficient for forward-bias |
- |
0.5 |
|
|
|
14 |
TNOM |
parameter measurement temperature |
°C |
27 |
50 |
|
|
|
|
|
|
|
|
| MOSFET Models (NMOS/PMOS) |
1 |
LEVEL |
model |
index |
- |
1 |
| LEVEL=1 -> Shichman-Hodges |
2 |
VTO |
zero-bias threshold voltage (VT0) |
V |
0.0 |
1.0 |
| LEVEL=2 -> MOS2 |
3 |
KP |
transconductance parameter |
A/V2 |
2.0e-5 |
3.1e-5 |
| LEVEL=3 -> MOS3, a semi-empirical model |
4 |
GAMMA |
Bitmap bulk threshold parameter () |
V1/2 |
0.0 |
0.37 |
| LEVEL=6 -> MOS6 |
5 |
PHI |
surface potential () |
V |
0.6 |
0.65 |
|
|
6 |
LAMBDA |
channel-length modulation (MOS1 and MOS2 only) |
1/V |
0.0 |
0.02 |
|
|
7 |
RD |
drain ohmic resistance |
Ohms |
0.0 |
1.0 |
|
|
8 |
RS |
source ohmic resistance |
Ohms |
0.0 |
1.0 |
|
|
9 |
CBD |
zero-bias B-D junction capacitance |
F |
0.0 |
20fF |
|
|
10 |
CBS |
zero-bias B-S junction capacitance |
F |
0.0 |
20fF |
|
|
11 |
IS |
bulk junction saturation current (IS) |
A |
1.0e-14 |
1.0e-15 |
|
|
12 |
PB |
bulk junction potential |
V |
0.8 |
0.87 |
|
|
13 |
CGSO |
gate-source overlap capacitance per meter channel width |
F/m |
0.0 |
4.0e-11 |
|
|
14 |
CGDO |
gate-drain overlap capacitance per meter channel width |
F/m |
0.0 |
4.0e-11 |
|
|
15 |
CGBO |
gate-bulk overlap capacitance per meter channel length |
F/m |
0.0 |
2.0e-10 |
|
|
16 |
RSH |
drain and source diffusion sheet resistance |
Ohms/q |
0.0 |
10.0 |
|
|
17 |
CJ |
zero-bias bulk junction bottom cap. per sq-meter of junction area |
F/m2 |
0.0 |
2.0e-4 |
|
|
18 |
MJ |
bulk junction bottom grading coeff. |
- |
0.5 |
0.5 |
|
|
19 |
CJSW |
zero-bias bulk junction sidewall cap. per meter of junction perimeter |
F/m |
0.0 |
1.0e-9 |
|
|
|
|
|
|
|
|
| LEVEL=4 -> BSIM |
1 |
VFB |
flat-band voltage |
V |
* |
|
|
|
2 |
PHI |
surface inversion potential |
V |
* |
|
|
|
3 |
K1 |
body effect coefficient |
V1/2 |
* |
|
|
|
4 |
K2 |
drain/source depletion charge-sharing coefficient |
- |
* |
|
|
|
5 |
ETA |
zero-bias drain-induced barrier-lowering coefficient |
- |
* |
|
|
|
6 |
MUZ |
zero-bias mobility |
cm2/V-s |
|
|
|
|
7 |
DL |
shortening of channel |
Bitmap m |
|
|
|
|
8 |
DW |
narrowing of channel |
Bitmap m |