记verilog实现counter的两种if-else表达方式

第一种：

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_ndl <= 16'd0;
        else 
            if(cs==WR_SEQ)
                if(fifo_pop_req)
                    counter_ndl <= counter_ndl - 16'd1;
                else
                    counter_ndl <= counter_ndl;
            else if(cs==BC_CIRC && counter_ndl==16'd0 && ch_circ==1'b1)
                    counter_ndl <= ch_ndl;
    end

第二种：

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_ndl <= 16'd0;
        else if(cs==WR_SEQ && fifo_pop_req)
            counter_ndl <= counter_ndl - 16'd1;
        else if(cs==BC_CIRC && counter_ndl==16'd0 && ch_circ==1'b1)
            counter_ndl <= ch_ndl;                  //load count value
    end

显然第二种更好。

第一种格式类似于人思维的直接表达，没经过加工和整理，初学者的常见写法，甚至有些多年经验的工程师也会出现这种写法。

第二种格式精确的概括了counter的两种状态：计数状态、加载初始值状态，并概括了两种状态的条件，更加接近电路的真实表达。

 

另附两个例子：

第一种：

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_pop <= 3'd0;
        else 
            if(cs==WR_SEQ)
                if(fifo_pop_req)
                    counter_pop <= counter_pop + 3'd1;
                else
                    counter_pop <= counter_pop;
            else
                    counter_pop <= 3'd0;
    end

第二种：

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            counter_pop <= 3'd0;
        else if(cs==WR_SEQ && fifo_pop_req)
            counter_pop <= counter_pop + 3'd1;
        else if(cs!=WR_SEQ)
            counter_pop <= 3'd0;
    end