OPENWRT-MTK-SDK 使用问题记录
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1、串口波特率修改
openwrt@OpenWRT:~/openwrt-sdk/20170518$ vim build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/linux-ramips_mt7620/linux-3.10.14/arch/mips/ralink/cmdline.c
39 #include
40 #include
41
42 #include
43
44 #if defined (CONFIG_RT2880_ROOTFS_IN_FLASH)
45 #ifdef CONFIG_SYSFS
46 char rt2880_cmdline[]="console=ttyS1,115200n8 root=/dev/mtdblock5";
47 #else
48 char rt2880_cmdline[]="console=ttyS1,115200n8 root=1f05";
49 #endif
50 #elif defined (CONFIG_RT2880_ROOTFS_IN_RAM)
51 char rt2880_cmdline[]="console=ttyS1,115200n8 root=/dev/ram0";
52 #else
53 #error "RT2880 Root File System not defined"
54 #endif 将其中的57600，修改为115200
2、SDK直接编译的固件 Kernel panic
[ 0.000000] node 0: [mem 0x00000000-0x03ffffff]
[ 0.000000] Primary instruction cache 64kB, 4-way, VIPT, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
[ 0.000000] Kernel command line: console=ttyS1,115200n8 root=/dev/mtdblock5 rootfstype=squashfs,jffs2 print-fatal-signals=1
[ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Writing ErrCtl register=0001ffe6
[ 0.000000] Readback ErrCtl register=0001ffe6
[ 0.000000] Memory: 61216k/65536k available (2599k kernel code, 4320k reserved, 657k data, 196k init, 0k highmem)
[ 0.000000] NR_IRQS:128
[ 0.000000] console [ttyS1] enabled
[ 0.096000] Calibrating delay loop... 385.02 BogoMIPS (lpj=770048)
[ 0.128000] pid_max: default: 32768 minimum: 301
[ 0.132000] Mount-cache hash table entries: 512
[ 0.136000] NET: Registered protocol family 16
[ 0.140000] RALINK_GPIOMODE = 1ab11c
[ 0.144000] RALINK_GPIOMODE = 18b11c
[ 0.144000] PPLL_CFG1=0x4010000
[ 0.148000] MT7620 PPLL unlock
[ 0.172000] bio: create slab at 0
[ 0.176000] Switching to clocksource Ralink Systick timer
[ 0.180000] NET: Registered protocol family 2
[ 0.188000] TCP established hash table entries: 512 (order: 0, 4096 bytes)
[ 0.192000] TCP bind hash table entries: 512 (order: -1, 2048 bytes)
[ 0.200000] TCP: Hash tables configured (established 512 bind 512)
[ 0.208000] TCP: reno registered
[ 0.208000] UDP hash table entries: 256 (order: 0, 4096 bytes)
[ 0.216000] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[ 0.224000] NET: Registered protocol family 1
[ 0.228000] MTK/Ralink EHCI/OHCI init.
[ 0.236000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.240000] jffs2: version 2.2. (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[ 0.252000] msgmni has been set to 119
[ 0.256000] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
[ 0.264000] io scheduler noop registered (default)
[ 0.268000] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[ 0.276000] serial8250: ttyS0 at MMIO 0x10000500 (irq = 37) is a 16550A
[ 0.284000] serial8250: ttyS1 at MMIO 0x10000c00 (irq = 12) is a 16550A
[ 0.292000] Ralink gpio driver initialized
[ 0.296000] Enable Ralink GDMA Controller Module
[ 0.300000] GDMA IP Version=3
[ 0.304000] spidrv_major = 217
[ 0.316000] brd: module loaded
[ 0.324000] deice id : ef 40 18 0 0 (40180000)
[ 0.328000] W25Q128BV(ef 40180000) (16384 Kbytes)
[ 0.332000] mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
[ 0.340000] Creating 5 MTD partitions on "raspi":
[ 0.348000] 0x000000000000-0x000001000000 : "ALL"
[ 0.352000] 0x000000000000-0x000000030000 : "Bootloader"
[ 0.360000] 0x000000030000-0x000000040000 : "Config"
[ 0.368000] 0x000000040000-0x000000050000 : "Factory"
[ 0.372000] 0x000000050000-0x000001000000 : "firmware"
[ 0.380000] rdm_major = 253
[ 0.384000] SMACCR1 -- : 0x00004c69
[ 0.388000] SMACCR0 -- : 0x6e75782d
[ 0.392000] Ralink APSoC Ethernet Driver Initilization. v3.1 512 rx/tx descriptors allocated, mtu = 1500!
[ 0.400000] SMACCR1 -- : 0x00004c69
[ 0.404000] SMACCR0 -- : 0x6e75782d
[ 0.408000] PROC INIT OK!
[ 0.412000] Ralink APSoC Hardware Watchdog Timer
[ 0.416000] TCP: cubic registered
[ 0.420000] NET: Registered protocol family 10
[ 0.428000] NET: Registered protocol family 17
[ 0.432000] 8021q: 802.1Q VLAN Support v1.8
[ 0.436000] VFS: Cannot open root device "mtdblock5" or unknown-block(0,0): error -6
[ 0.444000] Please append a correct "root=" boot option; here are the available partitions:
[ 0.456000] 1f00 16384 mtdblock0 (driver?)
[ 0.460000] 1f01 192 mtdblock1 (driver?)
[ 0.464000] 1f02 64 mtdblock2 (driver?)
[ 0.468000] 1f03 64 mtdblock3 (driver?)
[ 0.476000] 1f04 16064 mtdblock4 (driver?)
[ 0.480000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) 此问题为uboot与linux内核配置的分区大小不一致造成的，可修改uboot的源码配置分区大小，或修改LINUX的FLASH分区大小配置解决些问题，参考链接《XiaomiRouter自学之路(08-U-boot启动数值具体说明)》
openwrt@OpenWRT:~/openwrt-sdk/20170518$ vim build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/linux-ramips_mt7620/linux-3.10.14/drivers/mtd/maps/ralink-flash.h
1 #ifndef __RALINK_FLASH_H__
2 #define __RALINK_FLASH_H__
3
4 #if defined (CONFIG_RT2880_FLASH_32M)
5 #define MTD_BOOT_PART_SIZE 0x40000
6 #define MTD_CONFIG_PART_SIZE 0x20000
7 #define MTD_FACTORY_PART_SIZE 0x20000
8 #else
9 #if defined (RECONFIG_PARTITION_SIZE)
10 #if !defined (MTD_BOOT_PART_SIZE)
11 #error "Please define MTD_BOOT_PART_SIZE"
12 #endif
13 #if !defined (MTD_CONFIG_PART_SIZE)
14 #error "Please define MTD_CONFIG_PART_SIZE"
15 #endif
16 #if !defined (MTD_FACTORY_PART_SIZE)
17 #error "Please define MTD_FACTORY_PART_SIZE"
18 #endif
19 #else
// #define MTD_BOOT_PART_SIZE 0x30000
20 #define MTD_BOOT_PART_SIZE 0x20000
21 #define MTD_CONFIG_PART_SIZE 0x10000
22 #define MTD_FACTORY_PART_SIZE 0x10000
23 #endif
24 #endifopenwrt@OpenWRT:~/MT7620/uboot$ vim include/configs/rt2880.h
// #define CFG_BOOTLOADER_SIZE 0x20000
305 #define CFG_BOOTLOADER_SIZE 0x30000
306 #define CFG_CONFIG_SIZE 0x10000
307 #define CFG_FACTORY_SIZE 0x10000
308
309 #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_BOOTLOADER_SIZE)
310 #define CFG_FACTORY_ADDR (CFG_FLASH_BASE + CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE)
311 #define CFG_KERN_ADDR (CFG_FLASH_BASE + (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE))
312 #ifdef DUAL_IMAGE_SUPPORT
313 #define CFG_KERN2_ADDR (CFG_FLASH2_BASE + (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE))