fpga分模块(简单的模块调用)

顶层模块模块:

module structer(
input clk,
input rst,
output led,
output [2:0] led1
);

fash u1(
.clk(clk),
.rst_n(rst),
.led_out(led)
);


run u2(
.clk(clk),
.rst_n(rst),
.led_out(led1)
);

endmodule

闪光灯模块:

module fash(
input clk,
input rst_n,
output led_out
);

parameter times = 24'd10_000_000;  //21位

reg rled_out;
reg [23:0] count;//计数器

always @(posedge clk or negedge rst_n)
if(!rst_n)
count <= 24'b0;
else if(count == times)
count <= 24'b0;
else
count <= count + 1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n)
rled_out <= 1'b0;
else if(count == times)
rled_out <= ~rled_out;

assign led_out = rled_out; 

endmodule

流水灯模块:

module run(
input clk,
input rst_n,
output [2:0] led_out
);

parameter times = 25'd20_000_000; 
reg [24:0] count;

reg [2:0] rled_out;

always @(posedge clk or negedge rst_n)
if(!rst_n) 
count <= 25'b0;
else if(count == times)
count <= 25'b0;
else
count <= count +1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n)
rled_out <= 3'b100;
else if(count == times)
rled_out <= {rled_out[1:0],rled_out[2]};

assign led_out =  rled_out;

endmodule

心得:
①了解模块的调用方式
(书中有两种。本例是第二种,虽然麻烦点,但是楼主觉得量之间的对应关系十分明显,易于编程)
②项目的名称要和顶层的名称相同,不然报错
③多个模块是同时调用的
④在多个always中,不可以对同一reg量操作(例如进行赋值操作),程序报mix….错误
⑤1Mhz(1_000_000)是1微秒(注意自己定义的计数器是否可以达到自己设定的频率)

你可能感兴趣的:(verilog)