Design And Tool Flow (of Verilog HDL)

Introduction //简介

Various stages of ASIC/FPGA // ASIC（Application Specific Integrated Circuit ）/FPGA(Field Programming Gate Array) 设计的不同阶段

	Figure : Typical Design flow  // 典型的设计流图
	Specification               //规范说明，需求分析
	High Level Design      //上层设计
	Micro Design/Low level design //微观设计/底层设计
	RTL Coding              //RTL（Register Transfer Level，寄存器传输级）编码
	Simulation              //仿真
	Synthesis              //综合
	Place & Route      //布局、布线
	Post Silicon Validation  //后期的硅片验证

the above original link:http://www.asic-world.com/verilog/design_flow.html

Introduction  //简介

Being new to Verilog you might want to try some examples and try designing something new. I have listed the tool flow that could be used to achieve this. I have personally tried this flow and found this to be working just fine for me. Here I have taken only the front end design part and bits of FPGA design of the tool flow, that can be done without any fat money spent on tools.

作为Verilog HDL的一个新手，你也许想尝试一些例子并设计一些新的东西。我已经列出了用来实现这些功能的工具流图。我个人已经试用过这个工作流图，就我个人而言，发现其工作的非常好。这里我只讲前端设计的部分和一点工具流中FPGA设计，做这些不需要花费太多的钱在工具上。

Various stages of ASIC/FPGA  // ASIC（Application Specific Integrated Circuit ）/FPGA(Field Programming Gate Array) 设计的不同阶段

Specification : Word processor like Word, Kwriter, AbiWord, Open Office. 规范说明书，需求分析设计阶段：使用的工具：字处理器， 如像Word， Kwriter，AbiWord，Open Office等。 High Level Design : Word processor like Word, Kwriter, AbiWord, for drawing waveform use tools like waveformer or testbencher or Word, Open Office. 上层设计阶段：使用的工具：字处理器，如Word，Kwriter，AbiWord，OpenOffice等，为了画出波形图，需要使用诸如waveformer或者testbencher、World，Open office等类型的工具。 Micro Design/Low level design: Word processor like Word, Kwriter, AbiWord, for drawing waveform use tools like waveformer or testbencher or Word. 微观设计/底层设计阶段：使用的工具：字处理器，像Word，Kwriter，AbiWord等，为了画出波形图，需要使用诸如waveformer或者testbencher、World等类型的工具。 RTL Coding : Vim, Emacs, conTEXT, HDL TurboWriter RTL（Register Transfer Level，寄存器传输级）编码阶段： 使用的工具: Vim, Emacs, conTEXT, HDL TurboWriter Simulation : Modelsim, VCS, Verilog-XL, Veriwell, Finsim, Icarus. 仿真阶段：仿真工具 Modelsim, VCS, Verilog-XL, Veriwell, Finsim, Icarus. Synthesis : Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. You can download this from FPGA vendors like Altera and Xilinx for free. 综合阶段： 综合工具：Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. 可以从FPGA的供应商免费下载，如Altera、Xilinx。 Place & Route : For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic. 布局、布线阶段：对于FPGA可以使用FPGA供应商提供的P&R工具（布局、布线工具）。ASIC（专用集成电路工具）tool需要非常贵的—P&R的工具（布局、布线工具）如Apollo. 学生可以使用诸如LASI、Magic工具。 Post Si Validation : For ASIC and FPGA, the chip needs to be tested in real environment. Board design, device drivers needs to be in place. 后期的Si验证阶段：对于ASIC 和FPGA，芯片需要在正真实的环境中进行测试。板子设计（Board Design）、设备驱动需要到位。

		Figure : Typical Design flow //典型的设计流图
		Specification //规范说明书
		This is the stage at which we define what are the important parameters of the system/design that you are planning to design. A simple example would be: I want to design a counter; it should be 4 bit wide, should have synchronous reset, with active high enable; when reset is active, counter output should go to "0". 在这个阶段，我们定义我们设计的系统（设计）的重要参数。一个简单的例子是：我想设计一个计数器。 该计数器有4bi宽，还要有同步的复位（reset），高效的使能端；当复位被激活（置位）时，计数器（counter）将输出0.
		High Level Design  //上层设计
		This is the stage at which you define various blocks in the design and how they communicate. Let's assume that we need to design a microprocessor: high level design means splitting the design into blocks based on their function; in our case the blocks are registers, ALU, Instruction Decode, Memory Interface, etc. 在这个阶段，我们定义设计中的不同模块以及它们间的通信。假如我们需要设计一个微处理器：上层设计意味着基于功能将设计分解为几个不同的块； 在我们目前分解块包括：register（寄存器）、ALU（算术逻辑运算单元）、Instruction Decode（指令译码）、Memory Interface（存储器端口）等等。
		Figure : I8155 High Level Block Diagram //I8155上层设计的框图
		Micro Design/Low level design // 微观设计、底层设计
		Low level design or Micro design is the phase in which the designer describes how each block is implemented. It contains details of State machines, counters, Mux, decoders, internal registers. It is always a good idea to draw waveforms at various interfaces. This is the phase where one spends lot of time. 底层设计（或者微观设计）阶段，设计者描述每个block的具体实现。它包括状态机的细节、计数器、多路复用器、解码器、内部寄存器、 为各个不同的接口都画出波形图是不错的注意。 这是一个非常耗时的阶段。
		Figure : Sample Low level design //简单的底层设计图
		RTL Coding //RTL（Register Transfer Level, 寄存器传输级）编码
		In RTL coding, Micro design is converted into Verilog/VHDL code, using synthesizable constructs of the language. Normally we like to lint the code, before starting verification or synthesis. 在RTL 级的编码阶段， 微观的底层设计将转化为Verilog/VHDL 代码(使用语言中的可综合的构件)。通常，我们乐于在开始验证和综合前，先检验一下代码。
		1 module addbit ( 2 a , // first input 3 b , // Second input 4 ci , // Carry input 5 sum , // sum output 6 co // carry output 7 ); 8 //Input declaration 9 input a; 10 input b; 11 input ci; 12 //Ouput declaration 13 output sum; 14 output co; 15 //Port Data types 16 wire a; 17 wire b; 18 wire ci; 19 wire sum; 20 wire co; 21 //Code starts here 22 assign {co,sum} = a + b + ci; 23 24 endmodule // End of Module addbit You could download file addbit.v here
		Simulation // 仿真阶段
		Simulation is the process of verifying the functional characteristics of models at any level of abstraction. We use simulators to simulate the Hardware models. To test if the RTL code meets the functional requirements of the specification, we must see if all the RTL blocks are functionally correct. To achieve this we need to write a testbench, which generates clk, reset and the required test vectors. A sample testbench for a counter is shown below. Normally we spend 60-70% of time in design verification. 仿真是一个在不同的抽象层检验模型（model）的功能特性。我们使用仿真器对硬件模型进行仿真。 为了测试RTL级的编码是否满足系统设计中规范说明中功能要求， 我们认为RTL 功能模块是正确的。为了实现这个目的，我们需要写个能够产生时钟信号（clk）、复位信号（reset）、相关的测试向量的测试基准程序。 下面是一个关于计数器的一个简单的测试程序。通常，我们将花费60-70%的时间用于验证的设计（verification design）。
		Figure : Sample Testbench Env
		We use the waveform output from the simulator to see if the DUT (Device Under Test) is functionally correct. Most of the simulators come with a waveform viewer. As design becomes complex, we write self checking testbench, where testbench applies the test vector, then compares the output of DUT with expected values. 我们使用仿真器输出的波形图来查看待测设备（DUT， Device  Under Test)是否是功能上正确的。大多数仿真器都有一个波形图查看器。 当设计变得复杂时，我们需要设计一个自我校验的程序。自校验的程序能够使用测试向量，自动去比对待测试的设备的输出与其期望值(即常说的自动化测试)。
		There is another kind of simulation, called timing simulation, which is done after synthesis or after P&R (Place and Route). Here we include the gate delays and wire delays and see if DUT works at rated clock speed. This is also called as SDF simulation or gate level simulation. 还有另外一种仿真叫时间仿真，它在综合或者布局、布线之后进行。它包含门级时延和线时延，在相关的时钟频率下测试。 这个阶段的仿真也称之为 SDF-simulation 或者 gate level simulation。（SDF：Self-Defense Forces 自卫队）。
		Figure : 4 bit Up Counter Waveform //4位计数器的仿真波形图
		Synthesis  //综合
		Synthesis is the process in which synthesis tools like design compiler or Synplify take RTL in Verilog or VHDL, target technology, and constrains as input and maps the RTL to target technology primitives. Synthesis tool, after mapping the RTL to gates, also do the minimal amount of timing analysis to see if the mapped design is meeting the timing requirements. (Important thing to note is, synthesis tools are not aware of wire delays, they only know of gate delays). After the synthesis there are a couple of things that are normally done before passing the netlist to backend (Place and Route) 综合阶段，使用design compiler或者Synplify等综合工具将Verilog或VHDL等RTL级的代码和约束作为输入，同时将RTL编码映射为相关的目标技术原语。 综合工具在将RTL级代码转化为逻辑门电路后，还进行时间的最小化分析，以查看相关的分析能不能满足时间性要求。（值得注意的一点，综合工具没有考虑到线的延迟，只考虑了gate的延迟）。综合完成之后，和将网表（netlist）交付后端(backend, Place and Route）之前，还有许多事情要做。
		Formal Verification : Check if the RTL to gate mapping is correct. //形式化验证： 检验RTL到gate映射的正确性 Scan insertion : Insert the scan chain in the case of ASIC. 扫描插入：在ASIC中将插入扫描链。
		Figure : Synthesis Flow  //综合流图
		Place & Route //布局布线
		The gatelevel netlist from the synthesis tool is taken and imported into place and route tool in Verilog netlist format. All the gates and flip-flops are placed; clock tree synthesis and reset is routed. After this each block is routed. The P&R tool output is a GDS file, used by foundry for fabricating the ASIC. Backend team normally dumps out SPEF (standard parasitic exchange format) /RSPF (reduced parasitic exchange format)/DSPF (detailed parasitic exchange format) from layout tools like ASTRO to the frontend team, who then use the read_parasitic command in tools like Prime Time to write out SDF (standard delay format) for gate level simulation purposes. 从综合工具中产生的门级网表以Verilog网表的格式导入到布局布线工具中。所有的gate门和触发器将被布局，综合的时钟树，和复位信号被布线。在每个模块都走好线之后。布局、布线工具（P&R）将输出一个GDS file，用来生产加工ASIC。后端的工作组通常从布局工具（如ASTRO)转储为SPEF（standard parasitic exchange format，标准的寄生交换格式)或者 RSPF (reduced parasitic exchange format，精简的寄生交换格式)或者DSPF (detailed parasitic exchange format，具体化的寄生交换格式)交给前端team，前端组使用能够读取改格式的工具（ 如Prime Time）通过 read_parasitic命令读取，并输出门级仿真的SDF(standard delay format, 标准时延格式)。
		Figure : Sample micro-processor placement  //微处理器布局图样例
		Figure : J-K Flip-Flop //J-K触发器的布局布线图
		Post Silicon Validation  //后前的硅片验证
		Once the chip (silicon) is back from fab, it needs to be put in a real environment and tested before it can be released into Market. Since the simulation speed (number of clocks per second) with RTL is very slow, there is always the possibility to find a bug in Post silicon validation. 一旦芯片从加工工厂完成以后，在其投放市场之前，还需要进行真实环境下的测试。因为RTL级的仿真速度（频率）非常慢，所以在后期的硅片验证中总是有可能找到bug。

the original link: http://www.asic-world.com/verilog/design_flow1.html