练习四 阻塞语句和非阻塞语句

blocking模块代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    15:28:29 07/25/2019 
// Design Name: 
// Module Name:    blocking 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module blocking(
					clk,
					a,
					b,
					c
    );
	input clk;
	input [3:0]a;
	output [3:0]b,c;
	reg [3:0]b,c;
	always @(posedge clk)
		begin 
			b = a;
			c = b;
			$display("Blocking : a = %d , b = %d ,c = %d",a,b,c);
		end
	
endmodule

测试模块代码

`timescale 1ns / 100ps


// Company: 
// Engineer:
//
// Create Date:   15:48:47 07/25/2019
// Design Name:   blocking
// Module Name:   D:/FPGA/project/blocking_test/testbench/vtf_blocking_test.v
// Project Name:  blocking_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: blocking
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module vtf_blocking_test;

	// Inputs
	reg clk;
	reg [3:0] a;

	// Outputs
	wire [3:0] b;
	wire [3:0] c;

	// Instantiate the Unit Under Test (UUT)
	blocking uut (
		.clk(clk), 
		.a(a), 
		.b(b), 
		.c(c)
	);

	initial
		begin
			clk = 0;
			forever #50 clk = ~clk;
		end
		
	initial begin
		a = 4'h3;
		$display("____________________");
		#100	a = 4'h7;
		$display("____________________");
		#100	a = 4'hf;
		$display("____________________");
		#100	a = 4'ha;
		$display("____________________");
		#100	a = 4'h2;
		$display("____________________");
		#100	$display("____________________");
		$stop;	

	end
      
endmodule

结果与仿真波形

non_blocking模块代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    15:35:42 07/25/2019 
// Design Name: 
// Module Name:    non_blocking 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module non_blocking(
						clk,
						a,
						b,
						c
    );
	input clk;
	input [3:0]a;
	output [3:0]b,c;
	reg [3:0]b,c;
	always @(posedge clk)
		begin 
			b <= a;
			c <= b;
			$display("Non_Blocking :a=%d,b=%d,c=%d",a,b,c);
		end

endmodule

测试模块代码

同上

结果与仿真波形