基于FPGA的LED流水灯设计

1.首先分别建立建立两个模块div_clk和led_control。

div_clk模块：

module div_clk(clk,rst_n,clk_out);
input clk,rst_n;
output reg clk_out;

parameter DELAY =24'd999_999;
reg [23:0] cnt;
always @(posedge clk or negedge rst_n)
begin 
if(!rst_n)
cnt  <=24'd0;
else if (cnt==DELAY)
cnt <=24'd0;
else
cnt <=cnt+1'b1;
end
always@(posedge clk or negedge rst_n)
begin 
if(!rst_n)
clk_out <=1'd0;
else if(cnt ==DELAY)
  clk_out<=~clk_out;
end

endmodule

 

led_control模块：

module led_control(clk,rst_n,led_data);
input clk,rst_n;
output reg [7:0] led_data;
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst_n)
begin 
if(!rst_n)
current_state <=3'd0;
else 
current_state <=next_state;
end

always@(*)
begin 
case(current_state)
3'd0:next_state =3'd1;
3'd1:next_state =3'd2;
3'd2:next_state =3'd3;
3'd3:next_state =3'd4;
3'd4:next_state =3'd5;
3'd5:next_state =3'd6;
3'd6:next_state =3'd7;
3'd7:next_state =3'd0;
default:next_state =3'd0;
endcase
end

always@(*)
begin 
case(current_state)
3'd0:led_data <=8'b0000_0001;
3'd1:led_data <=8'b0000_0010;
3'd2:led_data <=8'b0000_0100;
3'd3:led_data <=8'b0000_1000;
3'd4:led_data <=8'b0001_0000;
3'd5:led_data <=8'b0010_0000;
3'd6:led_data <=8'b0100_0000;
3'd7:led_data <=8'b1000_0000;
default:led_data <=8'b0000_0001;
endcase
end
endmodule
2.根据上面两个模块建立原理图文件（.bdf）

3.全编译工程，后进行管脚配置，再利用EDA实验箱来进行实验的操作，观察实验现象，验证实验结果的正确性。