Vivado 2016.4 crash

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=IMPBD&message.id=17780

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=SYNTHBD&message.id=20441

https://www.xilinx.com/support/answers/68575.html

Description

In Vivado 2016.4, during implementation, Vivado hangs indefinitely or crashes after the place_design command is run:

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

This issue did not occur until Vivado 2016.3.

Note: This issue is specific to Windows Operating Systems.

Solution

This issue has been fixed in Vivado 2017.1.

The issue occurs when the IS_LOC_FIXED attribute is set to TRUE.

As a work-around, you can avoid this issue by using the following command after opt_design:

set_property is_loc_fixed false [get_ports -filter { IS_LOC_FIXED == "TRUE" } ]

However Bitgen's DRC requires the IS_LOC_FIXED property to be set to TRUE. 

As a result, you will need to restore the IS_LOC_FIXED TRUE property after place_design by reading the constraints file again using the following command:

read_xdc .xdc

Then run route_design and proceed with bitstream generation.

You can run implementation after synthesis using the following commands in tcl console:

opt_design

place_design

route_design

 

So as per the mentioned AR, use this command after opt_design:

set_property is_loc_fixed false [get_ports -filter { IS_LOC_FIXED == "TRUE" } ]

 Then run place_design.

Now run this:

read_xdc .xdc

Then run route_design.