armv8笔记--Chapter A1 Introduction to the ARMv8 Architecture

A load/store architecture, where data-processing operations only operate on register contents, not directly on
memory contents.

只能操作寄存器，不能直接操作内存

Simple addressing modes, with all load/store addresses determined from register contents and instruction
fields only.

SIMD全称Single Instruction Multiple Data，单指令多数据流，能够复制多个操作数，并把它们打包在大型寄存器的一组指令集。

以加法指令为例，单指令单数据（SISD）的CPU对加法指令译码后，执行部件先访问内存，取得第一个操作数；之后再一次访问内存，取得第二个操作数；随后才能进行求和运算。而在SIMD型的CPU中，指令译码后几个执行部件同时访问内存，一次性获得所有操作数进行运算。这个特点使SIMD特别适合于多媒体应用等数据密集型运算。

AArch64 The 64-bit Execution state. This Execution state:

• Provides 31 64-bit general-purpose registers, of which X30 is used as the procedure link
register.

• Provides a 64-bit program counter (PC), stack pointers (SPs), and exception link registers
(ELRs).

A1.4.2 Half-precision floating-point formats

• Defines the ARMv8 Exception model, with up to four Exception levels, EL0 - EL3, that
provide an execution privilege hierarchy

• Defines a number of Process state (PSTATE) elements that hold PE state. The A64
instruction set includes instructions that operate directly on various PSTATE elements.

A1.3.3 System registers

A1.3.4 ARMv8 Debug

Self-hosted debug
In this model, the PE generates debug exceptions. Debug exceptions are part of the ARMv8
Exception model.
External debug
In this model, debug events cause the PE to enter Debug state. In Debug state, the PE is controlled
by an external debugger.

All ARMv8 implementations support both models

A1.4 Supported data types

The ARMv8 architecture supports the following integer data types:
Byte 8 bits.
Halfword 16 bits.
Word 32 bits.
Doubleword 64 bits.
Quadword 128 bits.

A1.4.2 Half-precision floating-point formats

浮点数各个field占的位数

       

	sign	exponent	fraction
Harf precision	1	5	10
single precision	1	8	23
double precision	1	11	52

浮点数表示不是一个统一的公式，而是分成三段

0 < exponent < 0x1F    (–1)S × 2(exponent-15) × (1.fraction)

exponent == 0    (–1)S × 2–14 × (0.fraction)

exponent == 0x1F   NAN