1. 进行正常的时、分、秒计时功能,二十四小时制计时
2. 由数码管显示24h、60min、60s
3. 设置时间
4. 整点报时
5. 闹钟功能
该数字电子钟能够实现时、分、秒计时功能;校准时和分的功能;校准时间时秒清零的功能;整点报时的功能;
1. 秒计数是由一个六十进制的计数器构成,生成元器件如下
Clk:驱动秒计时器的时钟信号
Clr:校准时间时清零的输入端
En:使能端
Sec0[3..0]sec1[3..0]:秒的高位显示,低位显示
Co:进位输出端,作为分的clk输入
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port (clk,clr,en:in std_logic;
sec0,sec1:out std_logic_vector(3 downto 0);
co:outstd_logic);
end second;
architecture sec of second is
SIGNAL cnt1,cnt0:std_logic_vector(3 downto0);
begin
process(clk)
begin
if(clr='0')then
cnt0<="0000";
cnt1<="0000";
elsif(clk'eventand clk='1')then
if(en='1')then
ifcnt1="0101" and cnt0="1000" then
co<='1';
cnt0<="1001";
elsifcnt0<"1001" then
cnt0<=(cnt0+1);
else
cnt0<="0000";
ifcnt1<"0101"then
cnt1<=cnt1+1;
else
cnt1<="0000";
co<='0';
endif;
endif;
endif;
endif;
sec1<=cnt1;
sec0<=cnt0;
endprocess;
end sec;
Clk:设置分输入和秒进位的或输入
En:使能输入
Min1[3..0] min0[3..0]:分的高位显示,低位显示
Co:向时的进位输出
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port (clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:outstd_logic);
end minute;
architecture min of minute is
SIGNAL cnt1,cnt0:std_logic_vector(3 downto0);
begin
process(clk)
begin
if(clk'eventand clk='1')then
ifen='1' then
ifcnt1="0101" and cnt0="1001" then
co<='1';
cnt0<="0000";
cnt1<="0000";
elsifcnt0<"1001" then
cnt0<=(cnt0+1);
else
cnt0<="0000";
cnt1<=cnt1+1;
co<='0';
endif;
endif;
endif;
min1<=cnt1;
min0<=cnt0;
endprocess;
end min;
Clk:设置时间输入和分进位输入的或
en:使能端
h1[3..0] h0[3..0]:时的高位显示和低位显示
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end hour;
architecture beha of hour is
signal cnt1,cnt0:std_logic_vector(3 downto0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if en='1' then
if cnt1="0010" andcnt0="0011" then
cnt1<="0000";
cnt0<="0000";
elsif cnt0<"1001" then
cnt0<=cnt0+1;
else
cnt0<="0000";
cnt1<=cnt1+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;
end process;
end beha;
1. 按键去抖动,生成元器件如下
Clk:256hz频率输入
Reset:接GND
Din:接按键
Dout:输出传给按键选择器
代码如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity debounce is
port(clk,reset:in std_logic; --200HZ
din:in std_logic;
dout:out std_logic);
end debounce;
architecture a of debounce is
type state is(s0,s1,s2);
signal current:state;
begin
process(clk,reset,din)
begin
if(reset='1')then
current<=s0;
dout<='1';
elsif (clk'event and clk='1')then
case current is
when s0=>dout<='1';
if(din='0')then
current<=s1;
else
current<=s0;
end if;
when s1=>dout<='1';
if(din='0')then
current<=s2;
else
current<=s0;
end if;
when s2=>dout<='0';
if(din='0')then
current<=s2;
else
current<=s0;
end if;
when others=>dout<='1';
current<=s0;
end case;
end if;
end process;
end a;
Clk:16hz输入
Key1:按键调分的输入
Key2:按键调时的输入
Key3:按键秒清零的输入
Led1:输出信号给分元器件
Led2:输出信号给时元器件
Led3:输出清零信号给秒元器件
代码如下:libraryieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ctr1 is
port(clk:in std_logic; --10HZ
key1,key2,key3,key4:in std_logic;
led1,led2,led3,led4:out std_logic);
end ctr1;
architecture a of ctr1 is
begin
process (clk)
begin
if(clk'event and clk='1')then
if(key1='0')then
led1<='1';led2<='0';led3<='0';led4<='0';
elsif(key2='0')then
led1<='0';led2<='1';led3<='0';led4<='0';
elsif(key3='0')then
led1<='0';led2<='0';led3<='1';led4<='0';
elsif(key4='0')then
led1<='0';led2<='0';led3<='0';led4<='1';
else
led1<='0';led2<='0';led3<='0';led4<='0';
end if;
end if;
end process;
end a;
Clk2 clk:
En:使能输入
M1[3..0] m0[3..0]:接分的高位输出和低位输出
S1[3..0] s0[3..0]:接秒的高位输出和低位输出
Speaker:连接蜂鸣器
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xiang is
port(m1,m0,s1,s0:in std_logic_vector(3downto 0);
en,clk1,clk2,clk:in std_logic;
speaker:out std_logic);
end xiang;
architecture sss_arc of xiang is
begin
process(clk,clk1,clk2,m1,m0,s1,s0)
begin
if(en='1')then
speaker<=clk;
elsif(m1="0101"andm0="1001")then
if(s1="0101")then
if(s0="1001")then
speaker<=clk2;--1024HZ
elsif(s0="0001" ors0="0011" or s0="0101" or s0="0111")then
speaker<=clk1;--512HZ
end if;
else
speaker<='0';
end if;
elsif(m0<"1001" orm1<"0101"or s1<"0101")then
speaker<='0';
end if;
end process;
end sss_arc;
1. 模八的器件控制八个数码管显示的循环,生成元器件如下
Clk:输入
Clr:接GND
En:使能端
Y[2..0]:输出接数码管三个接受端
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mo8 is
port(clr,clk,en:in std_logic;
y:out std_logic_vector(2 downto 0));
end mo8;
architecture beha of mo8 is
signal p:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if en='1' then
if p="111" then
p<="000";
elsif p<"111" then
p<=p+1;
end if;
end if;
end if;
y<=p;
end process;
end beha;
Sel【2..0】:连接模八器件
M7[3..0] m6[3..0]:连接秒的高位和低位输出
M5[3..0]:接vcc(显示横)
M4[3..0] m3[3..0]:接分的高位和低位输出
M2[3..0]:接vcc(显示横)
M1[3..0] m0[3..0]:连接时的高位低位输出
Y[3..0]:输出给数码管显示
代码如下:
library ieee;
use ieee.std_logic_1164.all;
entity mux8_1 is
port(m0,m1,m2,m3,m4,m5,m6,m7:instd_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0));
end mux8_1;
architecture arc of mux8_1 is
begin
process(sel)
begin
case sel is
when"000"=>y<=m0;
when"001"=>y<=m1;
when"010"=>y<=m2;
when"011"=>y<=m3;
when"100"=>y<=m4;
when"101"=>y<=m5;
when"110"=>y<=m6;
when"111"=>y<=m7;
when others=>y<="XXXX";
end case;
end process;
end arc;
Num[3..0]:接收八选一的输出信号
Y[6..0]:驱动数码管显示
代码如下:libraryieee;
use ieee.std_logic_1164.all;
entity xianshi is
port(num:in std_logic_vector(3 downto 0);
y:out std_logic_vector(6 downto 0));
end xianshi;
architecture beha of xianshi is
begin
process(num)
begin
case num is
when"0000"=>y<="0111111";
when"0001"=>y<="0000110";
when"0010"=>y<="1011011";
when"0011"=>y<="1001111";
when"0100"=>y<="1100110";
when"0101"=>y<="1101101";
when"0110"=>y<="1111101";
when"0111"=>y<="0000111";
when"1000"=>y<="1111111";
when"1001"=>y<="1101111";
when others=>y<="1000000";
end case;
end process;
end beha;
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
-- q:out std_logic_vector(9downto 0);
clk512,clk4,clk1,clk16,clk256:out std_logic);
end fenpin;
architecture behave of fenpin is
signal y:std_logic_vector(9 downto 0);
begin
process(clk)
begin
if(clk='1')then
if(y="1111111111")then
y<="0000000000";
clk512<=y(0);
clk256<=y(1);
clk16<=y(5);
clk4<=y(7);
clk1<=y(9);
else
y<=y+'1';
clk512<=y(0);
clk256<=y(1);
clk16<=y(5);
clk4<=y(7);
clk1<=y(9);
end if;
end if;
end process;
end behave;
1. 比较器,比较当时显示时间与设置的闹钟时间是否相等,如相等,输出信号给蜂鸣器。生成元器件如下:
Clk clk1:使能输入
H0[3..0] h1[3..0]:闹钟设置时间的分输入
H3[3..0] h2[3..0]:闹钟设置时间的时输入
S0[3..0] s1[3..0]:现在时间的分的输入
S2[3..0] s3[3..0]:现在时间的时的输入
Y:输出信号给蜂鸣器
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bijiao2 is
port (clk,clk1:in std_logic;
h0,h1,h2,h3,s0,s1,s2,s3:in std_logic_vector(3downto 0);
y:outstd_logic);
end bijiao2;
architecture min of bijiao2 is
signal c:std_logic;
begin
process(clk,clk1,h0,h1,h2,h3,s0,s1,s2,s3)
begin
if(clk'event and clk='1')then
if h0(0)=s0(0)and h0(1)=s0(1)andh0(2)=s0(2)and h0(3)=s0(3) and h1(0)=s1(0)and h1(1)=s1(1)and h1(2)=s1(2)andh1(3)=s1(3) and h2(0)=s2(0)and h2(1)=s2(1)and h2(2)=s2(2)and h2(3)=s2(3)and h3(0)=s3(0)and h3(1)=s3(1)andh3(2)=s3(2)and h3(3)=s3(3) then
y<=clk1;
end if;
end if;
end process;
end min;
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