ODDR2

1.SPartan6 FPGA中， PLL产生的时钟不能直接连到FPGA的通用I/O上；

2.如果硬件已经连上了，可通过在PLL输出与通用I/O之间增加ODDR2模块缓冲来解决。

3.ODDR2与PLL模块可放在一个V文件中。

4.ODDR2模块如下：

  ODDR2 #(
    .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
    ) U_ODDR2_PLL输出时钟名 (
      .Q(oddr2_I/O管脚名),   // 1-bit DDR output data
      .C0(clock_PLL输出时钟名),   // 1-bit clock input
      .C1(~clock_PLL输出时钟名),   // 1-bit clock input
      .CE(1'b1), // 1-bit clock enable input
      .D0(1'b1), // 1-bit data input (associated with C0)
      .D1(1'b0), // 1-bit data input (associated with C1)
      .R(1'b0),   // 1-bit reset input
      .S(1'b0)    // 1-bit set input
    );

另外可参考《黑金Sparten6开发板Verilog教程V1.3》中

///调用 ODDR2 使时钟信号通过普通 IO 输出//
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(clk_out), // 1-bit DDR output data
.C0(pll_clk_o), // 1-bit clock input
.C1(~pll_clk_o), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule