HDLBits Verilog编程题134 PS/2数据传输状态机

当输入数据的in[7:0]的bit[3]=1时，开始接收数据；一次接收3字节的数据，存入输出out_bytes[23:0]，并使能接收完成done=1。

状态转换图
说明：现态state_c=Done时，若接收数据的bit[3]=1，则接收下一次的3字节数；若bit[3]=0则重新接收数据。

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

	parameter Byte1=0, Byte2=1, Byte3=2, Done=3;
    reg [2:0] state_c, state_n;
    wire Byte12Byte2, Byte22Byte3, Byte32Done, Done2Byte1, Done2Byte2;
    reg [7:0] data1, data2, data3;
    
    always@(posedge clk) begin
        if(reset)
            state_c <= Byte1;
        else begin
            state_c <= state_n;
        end
    end
    
    always@(*) begin
        case (state_c)
            Byte1:begin
                if(Byte12Byte2)
                    state_n = Byte2;
                else
                    state_n = state_c;
            end
            Byte2:begin
                if(Byte22Byte3)
                    state_n = Byte3;
            end
            Byte3:begin
                if(Byte32Done)
                    state_n = Done;
            end
            Done:begin
                if(Done2Byte1)
                    state_n = Byte1;
                else 
                    state_n = Byte2;
            end
        endcase 
    end
    assign Byte12Byte2 = in[3]==1;
    assign Byte22Byte3 = 1;
    assign Byte32Done = 1;
    assign Done2Byte1 = in[3]==0;
    
    always@(posedge clk) begin
        if(reset) begin
            data1<=0;
            data2<=0;
            data3<=0;
        end
        else begin
            if(state_c == Byte1)
                data1 <= in;
            else if(state_c == Byte2)
                data2 <= in;
            else if(state_c == Byte3)
                data3 <= in;
            else if(state_c == Done)
                data1 <= in;
            else begin
                data1<=0;
            	data2<=0;
            	data3<=0;
        	end
        end
    end
   
    assign done = state_c == Done;
    assign out_bytes = (state_c == Done)?{data1, data2, data3}:24'hZZZZZZ;

endmodule