hdlbits_Exams/2014_q3c

https://hdlbits.01xz.net/wiki/Exams/2014_q3c

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
	parameter S0=0,S1=1,S2=2,S3=3,S4=4;
    reg [2:0]Y1;
   
    always@(*)
        begin
            case(y)
                S0:Y1 = x?S1:S0;
                S1:Y1 = x?S4:S1;
                S2:Y1 = x?S1:S2;
                S3:Y1 = x?S2:S1;
                S4:Y1 = x?S4:S3;
            endcase
        end

    assign z = (y==S3)|(y==S4);
    assign Y0 = Y1[0];
endmodule