FPGA开发--Quartus II常见警告说明及解决方案

FPGA开发–Quartus II常见警告说明及解决方案
作者:Alex.Duan 日期:2017-04-01
文章摘要:
本文对Quartus II中常见的警告说明及解决方案的汇总。

Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder

处理方法:一般是模块例化接口不匹配,通过Connectivity Checks来查看错误原因

Table of Contents -->
Analysis & Synthesis -->
Connectivity Checks
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details.

警告(15714):某些引脚具有不完整的I/O分配。 有关详细信息,请参阅“I / O分配警告”报告.

原因说明:此警告主要是因为分配I/O引脚时,采用了默认的参数,主要是用来提醒懒人的,做为良好的设计习惯,一定要仔细对每一个管脚进行计算后,设置合理的参数,而不是简单用个默认值来搪塞;

处理方法::打开Pin Planner,选择current strength和slew rate的参数,将默认值改成非默认值;

Warning (169177): 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

警告(169177):2个引脚必须符合Altera对3.3,3.0和2.5 V接口的要求。 有关更多信息,请参考AN 447:使用3.3 / 3.0 / 2.5-V LVTTL / LVCMOS I / O系统连接Cyclone IV E器件。

原因说明:
这个警告很让人蛋疼,只是针对Cyclone IV E器件,要求设计者注意器件电平匹配的连接方法,而且还不能消除掉,对于不习惯于代码有警告的人来说,每次看到这个警告,心里就会有一万个羊驼呼啸而过…

Warning (35010): Previously generated Fitter netlist for partition “Top” is older than current Synthesis netlist – using the current Synthesis netlist instead to ensure that the latest source changes are included
Info (35011): Set the option to Ignore source file changes to force the Quartus II software to always use a previously generated Fitter netlist

处理方法:
Assignment–>Design Partition Window–>Netlist Type -->"Source File "

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