2021届秋招笔试题目记录
串并转换：valid有效输入数据，串并转换结束后，输出4位数据和valid信号；
1、串并转换主程序：
module serial2parrel (
input clk,
input rst_n,
input data_in,
input valid_in,
output reg[3:0] data_out,
output reg valid_out
);
always@(posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
data_out <= 4'd0;
end
else
begin
if(valid_in==1'b1)
begin
data_out <= {data_out[2:0],data_in};
end
else
begin
data_out <= data_out;
end
end
end
reg [2:0] cnt;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt <= 3'd0;
end
else
begin
if(valid_in==1'b1)
begin
if(cnt == 3'd3)
begin
cnt <= 3'd0;
valid_out <= 1'd1;
end
else
begin
cnt <= cnt + 1'd1;
valid_out <= 1'd0;
end
end
else
begin
cnt <= cnt;
valid_out <= 1'd0;
end
end
end
endmodule
测试文件：
`timescale 1 ns/1 ps
module tb;
reg sys_clk;
reg rst_n;
reg valid_in;
reg data_random;
wire [3:0] data_out;
wire valid_out;
initial
begin
sys_clk = 1'b0;
forever
#10 sys_clk= ~ sys_clk;
end
initial
begin
rst_n = 1'b0;
#50 rst_n = 1'b1;
end
initial
begin
valid_in = 1'b0;
forever
#20 valid_in= {$random}%2;
end
initial
begin
data_random = 1'd0;
forever
#20 data_random = {$random}%2;
end
initial begin
#5000;
$stop;
end
serial2parrel u1(
.clk(sys_clk),
.rst_n(rst_n),
.data_in(data_random),
.valid_in(valid_in),
.data_out(data_out),
.valid_out(valid_out)
);
endmodule
脚本.do文件：
quit -sim
vlog *.v
vsim -novopt ./work.tb //此命令代表仿真，不选择优化；work.tb；tb代表仿真module 名字
add wave sim:tb/u1/* //此命令代表添加波形，添加仿真文件中module名字/模块实例化名字
run -all
https://mp.weixin.qq.com/s?src=11×tamp=1597667424&ver=2528&signature=kk7NJAn-lxihQuAO-fWr4vsXzdKPC5A8cx6hJaxeImxMOobhHTyjqNbXfRec*XrKgda2xKRC6tCQu2AHiuaooHcBd9QUDNitbEjrc*Vpe1iQE12rWGGeCa8W5IWd2keM&new=1