使用xilinx最新工具vitis2019.2，定制zc702开发板linux系统

需要的工具

2019年10月9日，xilinx推出新一代FPGA集成开发工具——vitis，喜欢尝鲜的我，安装了vitis来进行FPGA开发。
　　我是嵌入式工程师出身，发现我的当前阶段的职业规划与老石《FPGA工程师最核心的就是全栈能力》（http://www.sohu.com/a/295982108_453160）基本一致，不论嵌入式工程师还是FPGA工程师，最后都要晋级为软硬件系统皆精通的全栈工程师（天下武功，殊途同归）。
　　全栈工程师就到头了吗？不，学海无涯啊。全栈工程师向上，还有算法全栈工程师（自己发明的名词，就是理解用户需求，将算力合理的分配套PS端和PL端，在全栈工程师基础上，具有算法硬件化的能力），数学工程师（在算法全栈工程师基础上，有了大量的工程实践，理解当前计算机体系架构背后的数学意义）。
　　闲话扯多了，回到正轨吧。在zynq系列（我使用zc702开发板，zynq7020的SOC）开发有操作系统的SOC系统，需要vitis工具（包含vivado2019.2、vivado_hls2019.2、vitis2019.2）和petalinux2019.2。
　　我的工具运行平台vitis安装在windows10上（vitis也可以安装在ubuntu上，我安装成功了，有两个问题，让我放弃了，第一，我的笔记本中ubuntu剩余空间太小了，不足安装；第二，vivado在ubuntu中运行正常，但vitis加载vivado生成的xsa文件失败，所以暂时放弃全linux环境开发zynq，后续争取全linux环境开发zynq）；petalinux安装在ubuntu16.04上（明年2020年准备升级为ubuntu20.04）。
　　vitis下载，下载地址：https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html，选择Xilinx Vitis 2019.2: All OS installer Single-File Download (TAR/GZIP - 30.76 GB) 文件，尽量不要使用web安装方式，方式网络通信失败导致多次安装。
　　petalinux下载，下载地址：https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html，选择PetaLinux 2019.2 Installer (TAR/GZIP - 7.92 GB) 文件。
　　vitis安装，基本就是下一步、下一步，里面有个选项，默认为vivado，更换为vitis即可，安装装包选择全部安装（也可根据自己需要进行更改）。安装完毕后，生成xilinx_vitis_ide2019.02、vivado2019.02、vivado_hls2019.02等。
　　petalinux安装，首先运行：sudo apt-get install -y python gawk gcc git make net-tools libncurses5-dev tftpd zlib1g:i386 libssl-dev flex bison libselinux1 gnupg wget diffstat chrpath socat xterm autoconf libtool tar unzip texinfo zlib1g-dev gcc-multilib build-essential libsdl1.2-dev libglib2.0-dev screen pax gzip chrpath socat texinfo gcc-multilib。安装必要的依赖包，然后运行./petalinux-v2019.2-final-installer.run，安装petalinux，按照提示安装即可，也很简单。
　　安装工具后，开始玩啥zc702吧。

定制自己的zc702包

vivado定制znyq7020板级描述

Petalinux2019.2需要Vivado2019.2提供的板级表述文件变为xsa文件（之前需要hdf文件）。
　　打开vivado2019.2工具，选择“open Example Project”->“Next”。
　　　选择“Base Zynq”->“Next”，建立zynq7020的工程。
　　自己填写工程名称、工程目录->“Next”，配置工程名称和要保存的目录位置。
　　选择zc702开发板->“Next”。
　　点击“Finish”完成工程建立。
　　新建工程状态，可以配置PS端连接状态。当前就不配置了，直接综合、布局布线生成xsa文件和bit文件。
　　点击“Generate Bitstream”进行综合和布局布线。
　　综合和布局布线完毕后。
　　导出*.xda板级描述文件和*.bit FPGA文件。
　　生成我们需要的zc702_demo.xda和zc702_demo.bit文件。

petalinux定制linux发行版

需要下载官方提供的zc702的linux的包，加上用vivado定制的zc702_demo.xda和zc702_demo.bit两个文件即可。
　　zc702的BSP包下载地址：https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html，下载 ZC702 BSP (BSP - 99.45 MB) 文件。
　　打开ubuntu的终端，收入指令输入指令：source /home/shirf/peta_linux/2019.2/settings.sh，是当前终端使用petalinux的工具。

　　使用zc702的BSP包生成linux工程包。输入指令：petalinux-create -t project -s setup_packet/xilinx-zc702-v2019.2-final.bsp。生成xilinx-zc702-2019.2工程目录。
　　
　　使用zc702_demo.xsa文件配置linux工程。输入指令：petalinux-config --get-hw-description=…/my_zc702_vivado_export。其中…/my_zc702_vivado_export包含zc702_demo.xsa文件。
　　

　　选择上图中的exit，不进行修改，使用默认配置。配置工程成功状态如下：
　
　　进行工程编译。输入指令：petalinux-build。进行整个工程的编译。编译成功后，在"image/linux"目录下，有烧写文件。

　
　　
　　生成BOOT.BIN文件，使用vivado生成的zc702_demo.bin文件，重命名为system.bit文件覆盖image/linux中system.bit文件。输入指令：etalinux-package --boot --format BIN --fsbl ./images/linux/zynq_fsbl.elf --fpga ./images/linux/system.bit --u-boot。将fsbl文件、bit文件、uboot文件，生成BOOT.BIN文件。至此，针对linux系统的烧写文件BOOT.BIN、image.ub、system.dtb文件都准备好了，存放在image/linux目录下。
　　

zc702启动自定制的linux系统

准备一张sd卡，我的为2G，使用fdisk命令分区，建立两个区，第一个区为200Mbyte、第二个区为剩下1.8Gbyte，第一个区会用fat32文件系统格式化、第二个区使用ext4文件系统格式化。具体方式参考xilinx的wiki（https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium#PrepareBootMedium-SDBoot中，SD BOOT部分）。将BOOT.BIN、image.ub、system.dtb放到第一个分区中（一定要为fat32格式，不然zynq内部的启动程序不认识其他分区）。

　　配置zc702从开发板启动（https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium#PrepareBootMedium-SDBoot中，SD BOOT部分），将SD卡插入zc702开发板中，启动电源，此时zc702正常启动linux系统，通过板载的usb转串口，在计算机上用minicom观察系统启动信息为，用户名为root，密码为root即可登录系统。
　　
U-Boot 2019.01 (Nov 27 2019 - 06:35:40 +0000) Xilinx Zynq ZC702

CPU: Zynq 7z020
Silicon: v0.0
Model: Zynq ZC702 Development Board
DRAM: ECC disabled 1 GiB
MMC: mmc@e0100000: 0
Loading Environment from SPI Flash… SF: Detected n25q128a with page size 256 B
*** Warning - bad CRC, using default environment

In: serial@e0001000
Out: serial@e0001000
Err: serial@e0001000
Model: Zynq ZC702 Development Board
Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
eth0: ethernet@e000b000
U-BOOT for xilinx-zc702-2019_2

ethernet@e000b000 Waiting for PHY auto negotiation to complete… TIMEOUT!
Hit any key to stop autoboot: 0
Device: mmc@e0100000
Manufacturer ID: 3
OEM: 5344
Name: SU02G
Bus Speed: 50000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: No
Capacity: 1.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
10953960 bytes read in 633 ms (16.5 MiB/s)
,## Loading kernel from FIT Image at 10000000 …
Using ‘[email protected]’ configuration
Verifying Hash Integrity … OK
Trying ‘kernel@1’ kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x10000104
Data Size: 4125936 Bytes = 3.9 MiB
Architecture: ARM
OS: Linux
Load Address: 0x00008000
Entry Point: 0x00008000
Hash algo: sha1
Hash value: 44ec07a1417655d9b39f1f90057d717e378a4fca
Verifying Hash Integrity … sha1+ OK
,## Loading ramdisk from FIT Image at 10000000 …
Using ‘[email protected]’ configuration
Verifying Hash Integrity … OK
Trying ‘ramdisk@1’ ramdisk subimage
Description: petalinux-user-image
Type: RAMDisk Image
Compression: gzip compressed
Data Start: 0x103f48d0
Data Size: 6805130 Bytes = 6.5 MiB
Architecture: ARM
OS: Linux
Load Address: unavailable
Entry Point: unavailable
Hash algo: sha1
Hash value: 006df8e566b1077a431ff8ff8f6b23c4ac323dd2
Verifying Hash Integrity … sha1+ OK
,## Loading fdt from FIT Image at 10000000 …
Using ‘[email protected]’ configuration
Verifying Hash Integrity … OK
Trying ‘[email protected]’ fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x103ef6f4
Data Size: 20762 Bytes = 20.3 KiB
Architecture: ARM
Hash algo: sha1
Hash value: 63cdb6f817b5faed1dde292b02a16e0f20cc1634
Verifying Hash Integrity … sha1+ OK
Booting using the fdt blob at 0x103ef6f4
Loading Kernel Image … OK
Loading Ramdisk to 07982000, end 07fff68a … OK
Loading Device Tree to 07979000, end 07981119 … OK

Starting kernel …

Booting Linux on physical CPU 0x0
Linux version 4.19.0-xilinx-v2019.2 (oe-user@oe-host) (gcc version 8.2.0 (GCC))9
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Zynq ZC702 Development Board
earlycon: cdns0 at MMIO 0xe0001000 (options ‘115200n8’)
bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x3f000000
random: get_random_bytes called from start_kernel+0x80/0x3c4 with crng_init=0
percpu: Embedded 16 pages/cpu @(ptrval) s35916 r8192 d21428 u65536
Built 1 zonelists, mobility grouping on. Total pages: 260608
Kernel command line: console=ttyPS0,115200 earlycon
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1006284K/1048576K available (6144K kernel code, 204K rwdata, 1604K roda)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0x(ptrval) - 0x(ptrval) (7136 kB)
.init : 0x(ptrval) - 0x(ptrval) (1024 kB)
.data : 0x(ptrval) - 0x(ptrval) ( 205 kB)
.bss : 0x(ptrval) - 0x(ptrval) ( 133 kB)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af02s
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537s
timer #0 at (ptrval), irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency… 666.)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs …
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191s
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 27, base_baud = 3125000) is as
console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [cdns0] disabled
bootconsole [cdns0] disabled
GPIO IRQ not connected
XGpio: gpio@41200000: registered, base is 1020
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs…
Freeing initrd memory: 6648K
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Eve6
brd: module loaded
loop: module loaded
m25p80 spi0.0: found n25q128a11, expected n25q512a
m25p80 spi0.0: n25q128a11 (16384 Kbytes)
3 fixed-partitions partitions found on MTD device spi0.0
Creating 3 MTD partitions on “spi0.0”:
0x000000000000-0x000000500000 : “boot”
0x000000500000-0x000000520000 : “bootenv”
0x000000520000-0x000000fa0000 : “kernel”
libphy: Fixed MDIO Bus: probed
CAN device driver interface
libphy: MACB_mii_bus: probed
Marvell 88E1116R e000b000.ethernet-ffffffff:07: attached PHY driver [Marvell 88)
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (0)
e1000e: Intel® PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright© 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 ‘Enhanced’ Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regr
chipidea-usb2 e0002000.usb: Linked as a consumer to regulator.0
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 24
si570 1-005d: registered, current frequency 148500000 Hz
i2c i2c-0: Added multiplexed i2c bus 1
i2c i2c-0: Added multiplexed i2c bus 2
at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 3
i2c i2c-0: Added multiplexed i2c bus 4
rtc-pcf8563 5-0051: rtc core: registered rtc-pcf8563 as rtc0
i2c i2c-0: Added multiplexed i2c bus 5
i2c i2c-0: Added multiplexed i2c bus 6
i2c i2c-0: Added multiplexed i2c bus 7
i2c i2c-0: Added multiplexed i2c bus 8
pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
ucd9200 8-0034: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0034: 4 rails configured
random: fast init done
ucd9200 8-0035: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0035: 4 rails configured
ucd9200 8-0036: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0036: 2 rails configured
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright© Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: Invalid maximum block size, assuming 512 bytes
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20170425 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20170425)
can: broadcast manager protocol (rev 20170425 t)
can: netlink gateway (rev 20170425) max_hops=1
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
input: gpio-keys as /devices/soc0/gpio-keys/input/input0
rtc-pcf8563 5-0051: setting system clock to 2019-11-27 06:53:12 UTC (1574837592)
of_cfs_init
of_cfs_init: OK
ALSA device list:
No soundcards found.
Freeing unused kernel memory: 1024K
Run /init as init process
INIT: mmc0: new high speed SD card at address e624
mmcblk0: mmc0:e624 SU02G 1.84 GiB
version 2.88 booting mmcblk0: p1 p2

Starting udev
udevd[817]: starting version 3.2.5
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[818]: starting eudev-3.2.5
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt.
urandom_read: 4 callbacks suppressed
random: dd: uninitialized urandom read (512 bytes read)
INIT: Entering runlevel: 5
Configuring network interfaces… IPv6: ADDRCONF(NETDEV_UP): eth0: link is not y
udhcpc: started, v1.29.2
udhcpc: sending discover
udhcpc: sending discover
udhcpc: sending discover
udhcpc: no lease, forking to background
done.
Starting haveged: haveged: listening socket at 3
haveged: haveged starting up

Starting Dropbear SSH server: random: dropbearkey: uninitialized urandom read ()
random: dropbearkey: uninitialized urandom read (32 bytes read)
Generating 2048 bit rsa key, this may take a while…
haveged: haveged: ver: 1.9.4; arch: generic; vend: ; build: (gcc 8.2.0 CTV); coK

haveged: haveged: cpu: (VC); data: 16K (D); inst: 16K (D); idx: 12/40; sz: 15018

haveged: haveged: tot tests(BA8): A:1/1 B:1/1 continuous tests(B): last entrop4

haveged: haveged: fills: 0, generated: 0

random: crng init done
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQC00SMqxrPbN8DRIpBygHQKAF64JT30i+CJprjzaug2
Fingerprint: sha1!! 56:ba:78:8d:a9:94:26:47:6d:06:c4:25:9233:4b:b4:3e:50:13
dropbear.
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2019.2 xilinx-zc702-2019_2 /dev/ttyPS0

xilinx-zc702-2019_2 login: root
Password:
root@xilinx-zc702-2019_2:~# cd /
root@xilinx-zc702-2019_2:/# ls
bin dev home lib mnt root sbin tmp var
boot etc init media proc run sys usr
root@xilinx-zc702-2019_2:/#

小结和后续工作

1、通过上述步骤，完成zynq7020整套开发环境搭建的验证。后续工作在此基础上继续进行。
2、接下的的工作分享。
（1）当前系统无法上电自启动自定义的脚本，应为即使配置了/etc中的启动选项，由于是ramdisk的文件系统，重新上电后，之前的配合都还原了。我们要保留ramdisk文件系统，这样安全可靠啊，同时启动自定义的脚本，这就需要我们在以后rootfs根文件系统目录的基础上，编译/etc中相应脚本，然后将rootfs制作成.cpio格式，然后编译内核时指定ramdisk为我们制作的.cpio文件系统。
（2）利用petalinux工具，添加像python等第三方工具，丰富我们的发行版。
（3）使用vitis调试linux的应用程序hello_world。尝鲜vitis这个集成开发环境。
（4）vivado配置我们的ps端，使能更多内部硬核。
（5）使用vivado_hls工具，自定制软IP核，挂接到PS端，编写驱动，来一场正经的zynq开发。（我是嵌入式工程师，对vhdl不熟，那我就用xilinx为嵌入式工程师准备的hls工具，使用C/C++语言开发FPGA吧）