MIPS(pipeline+harzard)

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/23 15:31:35
// Design Name: 
// Module Name: MIPS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module MIPS(
input clk,
input rst
    );
reg [31:0] RegFile [0:31];
reg [31:0] IMEM [0:255];
reg [31:0] DMEM [0:255];

integer i;
initial
begin
    for(i=0;i<256;i=i+1)
        DMEM[i]=i;
end

initial
begin
    for(i=0;i<32;i=i+1)
        RegFile[i]<=i;
end

initial
begin
    IMEM[0]=32'h10000003;
    IMEM[4]=32'h00430820;
    IMEM[8]=32'h00a62022;
    IMEM[12]=32'h8d070004;
    IMEM[16]=32'h00e84820;
    IMEM[20]=32'h01280822;
    IMEM[24]=32'h01491020;
    IMEM[28]=32'had09fffc;
    IMEM[32]=32'h01495820;
    IMEM[36]=32'h8c0c0004;
    IMEM[40]=32'h018d7020;
    IMEM[44]=32'h8e8f0000;
    IMEM[48]=32'hae8f0004;
end

wire IF2ID_Write;
wire PCWrite;
wire ID2EXE_Stall;
wire [31:0]ALUSrcA;                  
wire [31:0]ALUSrcB;
wire [1:0]ForwardA;
wire [1:0]ForwardB;
wire [4:0]IF2ID_rs;
wire [4:0]IF2ID_rt;
wire [31:0]MEM2WB_Data;
wire FlushIF;
wire FlushID;
wire FlushEXE;

assign FlushIF=(EXE2MEM_Branch==1'b1&&EXE2MEM_ALUOut==1'b0)?1'b1:1'b0;           //若发生分支，则flush之前的3条指令
assign FlushID=(EXE2MEM_Branch==1'b1&&EXE2MEM_ALUOut==1'b0)?1'b1:1'b0;
assign FlushEXE=(EXE2MEM_Branch==1'b1&&EXE2MEM_ALUOut==1'b0)?1'b1:1'b0;

//IF
reg [31:0] PC;
reg [31:0] IF2ID_NPC;
reg [31:0] IF2ID_IR;
//ID
reg [4:0]ID2EXE_rs;                //Rs寄存器号 约定大写为数据，小写为寄存器�?
reg [4:0]ID2EXE_rt;                //Rt寄存器号
reg [4:0]ID2EXE_rd;                //Rd寄存器号
reg [31:0]ID2EXE_Rs;               //Rs寄存器内�?
reg [31:0]ID2EXE_Rt;               //Rt寄存器内�?
reg [31:0]ID2EXE_Imm;              //符号扩展后的立即�?
reg [31:0]ID2EXE_NPC;                  

reg ID2EXE_RegDst;
reg ID2EXE_ALUSrc;
reg ID2EXE_MemRead;
reg ID2EXE_MemWrite;
reg ID2EXE_Branch;
reg ID2EXE_MemtoReg;
reg ID2EXE_RegWrite;
reg [1:0] ID2EXE_ALUOp;
//EXE
reg [31:0]EXE2MEM_ALUOut;
reg [31:0]EXE2MEM_BranchPC;
reg [31:0]EXE2MEM_Rt;
reg [4:0]EXE2MEM_RegRd;                    //WB阶段写寄存器�?

reg EXE2MEM_MemRead;
reg EXE2MEM_MemWrite;
reg EXE2MEM_Branch;
reg EXE2MEM_MemtoReg;
reg EXE2MEM_RegWrite;
//MEM
reg [31:0]MEM2WB_LDM;
reg [31:0]MEM2WB_ALUOut;
reg [4:0]MEM2WB_RegRd;

reg MEM2WB_RegWrite;
reg MEM2WB_MemtoReg;

/****************************************************************************************/

assign IF2ID_rs=IF2ID_IR[25:21];
assign IF2ID_rt=IF2ID_IR[20:16];
assign MEM2WB_Data=(MEM2WB_MemtoReg)?MEM2WB_LDM:MEM2WB_ALUOut;

//IF
always@(posedge clk,posedge rst)
begin
if(rst)
begin
    PC<=32'd0;
    IF2ID_NPC<=32'd0;
    IF2ID_IR<=32'd0;
end
else
begin
    if(PCWrite)
        if(EXE2MEM_Branch==1'b1&&EXE2MEM_ALUOut==1'b0)
            PC<=EXE2MEM_BranchPC;
        else
            PC<=PC+4;
    else
        PC<=PC;
    if(FlushIF)
    begin
        IF2ID_NPC<=32'd0;
        IF2ID_IR<=32'd0;
    end
    else if(IF2ID_Write)
    begin
        IF2ID_NPC<=PC+4;
        IF2ID_IR<=IMEM[PC];
    end
    
    else
    begin
        IF2ID_NPC<=IF2ID_NPC;
        IF2ID_IR<=IF2ID_IR;
    end
end
end

//ID
HAZARD_DETECTION U1(
.ID2EXE_MemRead(ID2EXE_MemRead),
.IF2ID_rs(IF2ID_rs),
.IF2ID_rt(IF2ID_rt),
.ID2EXE_rt(ID2EXE_rt),
.PCWrite(PCWrite),
.ID2EXE_Stall(ID2EXE_Stall),
.IF2ID_Write(IF2ID_Write)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else if(ID2EXE_Stall||FlushID)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else
case(IF2ID_IR[31:26])
6'b000000:begin
    {
     ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b100100010;
end
6'b100011:begin
    {
     ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b011110000;
end
6'b101011:begin
    {
     ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b010001000;
end
6'b000100:begin
    {
     ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000101;
end
default:
    {
     ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000000;
endcase

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else if(FlushID)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else
begin
    ID2EXE_rs<=IF2ID_IR[25:21];
    ID2EXE_rt<=IF2ID_IR[20:16];
    ID2EXE_rd<=IF2ID_IR[15:11];
    ID2EXE_Rs<=RegFile[IF2ID_IR[25:21]];
    ID2EXE_Rt<=RegFile[IF2ID_IR[20:16]];
    ID2EXE_Imm<={
     {
     16{
     IF2ID_IR[15]}},IF2ID_IR[15:0]};
    ID2EXE_NPC<=IF2ID_NPC;
end

//EXE

FORWARDING U2(
.ID2EXE_rs(ID2EXE_rs),
.ID2EXE_rt(ID2EXE_rt),
.EXE2MEM_RegRd(EXE2MEM_RegRd),
.MEM2WB_RegRd(MEM2WB_RegRd),
.EXE2MEM_RegWrite(EXE2MEM_RegWrite),
.MEM2WB_RegWrite(MEM2WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
//ALUSrcA三�?�一
mux3_1 U3(
.a(ID2EXE_Rs),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardA),
.out(ALUSrcA)
);
//ALUSrcB
mux3_1 U4(
.a(ID2EXE_Rt),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardB),
.out(ALUSrcB)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else if(FlushEXE)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else
begin
    EXE2MEM_MemRead<=ID2EXE_MemRead;
    EXE2MEM_MemWrite<=ID2EXE_MemWrite;
    EXE2MEM_Branch<=ID2EXE_Branch;
    EXE2MEM_MemtoReg<=ID2EXE_MemtoReg;
    EXE2MEM_RegWrite<=ID2EXE_RegWrite;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_ALUOut<=32'd0;
    EXE2MEM_RegRd<=5'd0;
    EXE2MEM_Rt<=32'd0;
    EXE2MEM_BranchPC<=32'd0;
end
else
begin
    EXE2MEM_RegRd<=(ID2EXE_RegDst)?ID2EXE_rd:ID2EXE_rt;
    EXE2MEM_Rt<=ALUSrcB;               //ID2EXE_Rt or forwarded from EXE2MEM or forwarded from MEM2WB
    EXE2MEM_BranchPC<=ID2EXE_NPC+(ID2EXE_Imm<<2);
    case(ID2EXE_ALUOp)
        2'b00:EXE2MEM_ALUOut<=ALUSrcA+ID2EXE_Imm;          //lw or sw
        2'b01:EXE2MEM_ALUOut<=ALUSrcA-ALUSrcB;
        2'b10:
        case (ID2EXE_Imm[5:0])
            6'b100000:EXE2MEM_ALUOut<=ALUSrcA+ALUSrcB;
            6'b100010:EXE2MEM_ALUOut<=ALUSrcA-ALUSrcB;
            6'b100100:EXE2MEM_ALUOut<=ALUSrcA&ALUSrcB;
            6'b100101:EXE2MEM_ALUOut<=ALUSrcA|ALUSrcB;
            6'b101010:EXE2MEM_ALUOut<=(ALUSrcA<ALUSrcB)?1:0;
        default: EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
        endcase
        default:
            EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
    endcase
end

//MEM
always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_RegWrite<=1'b0;
    MEM2WB_MemtoReg<=1'b0;
end
else
begin
    MEM2WB_RegWrite<=EXE2MEM_RegWrite;
    MEM2WB_MemtoReg<=EXE2MEM_MemtoReg;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_LDM<=32'd0;
    MEM2WB_ALUOut<=32'd0;
    MEM2WB_RegRd<=5'd0;
end
else
begin
    MEM2WB_ALUOut<=EXE2MEM_ALUOut;
    MEM2WB_RegRd<=EXE2MEM_RegRd;
    if(EXE2MEM_MemRead)
        MEM2WB_LDM<=DMEM[EXE2MEM_ALUOut];
    else if(EXE2MEM_MemWrite)
        DMEM[EXE2MEM_ALUOut]<=EXE2MEM_Rt;
end

//WB
always@(negedge clk,posedge rst)
if(rst)
    ;
else if(MEM2WB_RegWrite)
    if(MEM2WB_MemtoReg)
        RegFile[MEM2WB_RegRd]<=MEM2WB_LDM;
    else
        RegFile[MEM2WB_RegRd]<=MEM2WB_ALUOut;
        
endmodule

hazard模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:44:46
// Design Name: 
// Module Name: HAZARD_DETECTION
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module HAZARD_DETECTION(
input ID2EXE_MemRead,
input [4:0]ID2EXE_rt,
input [4:0]IF2ID_rs,
input [4:0]IF2ID_rt,
output reg PCWrite,
output reg IF2ID_Write,
output reg ID2EXE_Stall
    );
always@(*)
begin
if(ID2EXE_MemRead&&((ID2EXE_rt==IF2ID_rs)||(ID2EXE_rt==IF2ID_rt)))               //流水线阻塞1个clk
begin
    ID2EXE_Stall=1'b1;                                  //ID2EXE段的控制命令清0                           
    PCWrite=1'b0;                                       //PC保持不变
    IF2ID_Write=1'b0;                                   //IF2ID段寄存器保持不变
end
else
begin
    ID2EXE_Stall=1'b0;
    PCWrite=1'b1;
    IF2ID_Write=1'b1;
end
end

endmodule

forwarding模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:30:49
// Design Name: 
// Module Name: FORWARDING
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module FORWARDING(
input [4:0]ID2EXE_rs,
input [4:0]ID2EXE_rt,
input [4:0]EXE2MEM_RegRd,
input [4:0]MEM2WB_RegRd,
input EXE2MEM_RegWrite,
input MEM2WB_RegWrite,
output reg [1:0]ForwardA,
output reg [1:0]ForwardB
);
//ForwardA
always@(*)
begin
if(EXE2MEM_RegWrite==1&&(EXE2MEM_RegRd!=0)&&EXE2MEM_RegRd==ID2EXE_rs)
    ForwardA=2'b10;                                       // 来自EXE/MEM
else if(MEM2WB_RegWrite==1&&(MEM2WB_RegRd!=0)&&MEM2WB_RegRd==ID2EXE_rs)
    ForwardA=2'b01;                                       // 来自MEM/WB
else
    ForwardA=2'b00;                                       // 来自ID/EXE
end                                                      
//ForwardB
always@(*)
begin
if(EXE2MEM_RegWrite==1&&(EXE2MEM_RegRd!=0)&&EXE2MEM_RegRd==ID2EXE_rt)
    ForwardB=2'b10;
else if(MEM2WB_RegWrite==1&&(MEM2WB_RegRd!=0)&&MEM2WB_RegRd==ID2EXE_rt)
    ForwardB=2'b01;
else
    ForwardB=2'b00;
end

endmodule

mux模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/24 10:55:12
// Design Name: 
// Module Name: mux3_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module mux3_1(
input [31:0]a,
input [31:0]b,
input [31:0]c,
input [1:0]select,
output reg [31:0]out
    );
always@(*)
case (select)
    2'b00:out=a;
    2'b10:out=b;
    2'b01:out=c; 
    default:out=32'd0;
endcase
endmodule