2020-12-28

数字逻辑实验

数码管显示控制器

LIBRARY IEEE ;
 USE IEEE.STD_LOGIC_1164.ALL ;
 ENTITY DECL7S IS
  PORT ( A  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
      LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  ) ;
 END ;
 ARCHITECTURE one OF DECL7S IS
 BEGIN
  PROCESS( A )
  BEGIN
  CASE  A  IS
   WHEN "0000" =>  LED7S <= "0111111" ; 
   WHEN "0001" =>  LED7S <= "0000110" ; 
   WHEN "0010" =>  LED7S <= "1011011" ; 
   WHEN "0011" =>  LED7S <= "1001111" ; 
   WHEN "0100" =>  LED7S <= "1100110" ; 
   WHEN "0101" =>  LED7S <= "1101101" ; 
   WHEN "0110" =>  LED7S <= "1111101" ;
   WHEN "0111" =>  LED7S <= "0000111" ;
   WHEN "1000" =>  LED7S <= "1111111" ; 
   WHEN "1001" =>  LED7S <= "1101111" ; 
   WHEN "1010" =>  LED7S <= "1110111" ; 
   WHEN "1011" =>  LED7S <= "1111100" ;
   WHEN "1100" =>  LED7S <= "0111001" ;
   WHEN "1101" =>  LED7S <= "1011110" ; 
   WHEN "1110" =>  LED7S <= "1111001" ;
   WHEN "1111" =>  LED7S <= "1110001" ;
   WHEN OTHERS =>  NULL ;
   END CASE ;
  END PROCESS ;
 END ; 

数字时钟

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS                             
    PORT (    CLK : IN STD_LOGIC;
	        Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                cout:out bit);
END CNT10;
ARCHITECTURE behav OF CNT10 IS
    SIGNAL COUNT : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
    PROCESS( CLK )
    BEGIN
        IF CLK'EVENT AND CLK = '1' THEN
           COUNT <= COUNT + 1;
           cout<='0';
        end if;
        if count="1010" then
           count<="0000";
           cout<='1';
        END IF;
	Q  <= COUNT;
    END PROCESS;
END behav;

彩灯控制器

library ieee;
use ieee.std_logic_1164.all;

entity jishuqi is
     port(clock:in std_logic;
          countnum:buffer integer range 0 to 23          
);
end entity jishuqi;

architecture behavior of jishuqi is
begin
     process(clock)
     begin
		if rising_edge(clock) then
			if(countnum=23) then
				countnum<=0;
		    else
				countnum<=countnum+1;
			end if;
		end if;
	end process;
end behavior;

LIBRARY IEEE ;
 USE IEEE.STD_LOGIC_1164.ALL ;
 ENTITY yimaqi IS
  PORT ( A  : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
      yima : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  ) ;
 END ;
 ARCHITECTURE one OF yimaqi IS
 BEGIN
  PROCESS( A )
  BEGIN
  CASE  A  IS
   WHEN "00000" =>  yima <= "10000001" ; 
   WHEN "00001" =>  yima <= "11000011" ; 
   WHEN "00010" =>  yima <= "11100111" ; 
   WHEN "00011" =>  yima <= "11111111" ; 
   WHEN "00100" =>  yima <= "11100111" ; 
   WHEN "00101" =>  yima <= "11000011" ; 
   WHEN "00110" =>  yima <= "10000001" ;
   WHEN "00111" =>  yima <= "00000000" ;
   WHEN "01000" =>  yima <= "10000000" ; 
   WHEN "01001" =>  yima <= "11000000" ; 
   WHEN "01010" =>  yima <= "11100000" ; 
   WHEN "01011" =>  yima <= "11110000" ;
   WHEN "01100" =>  yima <= "11111000" ;
   WHEN "01101" =>  yima <= "11111100" ; 
   WHEN "01110" =>  yima <= "11111110" ;
   WHEN "01111" =>  yima <= "11111111" ;
   WHEN "10000" =>  yima <= "11111110" ;
   WHEN "10001" =>  yima <= "11111100" ;
   WHEN "10010" =>  yima <= "11111000" ;
   WHEN "10011" =>  yima <= "11110000" ;
   WHEN "10100" =>  yima <= "11100000" ;
   WHEN "10101" =>  yima <= "11000000" ;
   WHEN "10110" =>  yima <= "10000000" ;
   WHEN "10111" =>  yima <= "00000000" ;
   WHEN OTHERS =>  NULL ;
   END CASE ;
  END PROCESS ;
 END ; 

交通灯控制器

library ieee;
use ieee.std_logic_1164.all;

entity controller is
     port(clock:in std_logic;
          hold:in std_logic;
          countnum:in integer range 0 to 59;
          numa,numb:out integer range 0 to 30;
reda,greena,yellowa:out std_logic;
redb,greenb,yellowb:out std_logic;
            flash:out std_logic
);
end entity controller;

architecture behavior of controller is
begin
     process(clock)
     begin
		if falling_edge(clock) then
			if hold='1' then
				reda<='1';
				redb<='1';
				greena<='0';
				greenb<='0';
				yellowa<='0';
				yellowb<='0';
				flash<='1';
			else
			    flash<='0';
				if(countnum<=29) then
					numa<=30-countnum;
					reda<='0';
					greena<='1';
					yellowa<='0';
				elsif (countnum<=34) then
					numa<=35-countnum;
					reda<='0';
					greena<='0';
					yellowa<='1';
				else
					numa<=60-countnum;
					reda<='1';
					greena<='0';
					yellowa<='0';
				end if;
				if(countnum<=24) then
					numb<=25-countnum;
					redb<='1';
					greenb<='0';
					yellowb<='0';
				elsif (countnum<=54) then
					numb<=55-countnum;
					redb<='0';
					greenb<='1';
					yellowb<='0';
				else
				    numb<=60-countnum;
					redb<='0';
					greenb<='0';
					yellowb<='1';
				end if;
			end if;
		end if;
	end process;
end behavior;

library ieee;
use ieee.std_logic_1164.all;

entity counter is
	port(clk:in std_logic;
	     reset:in std_logic;
	     hold:in std_logic;
	     num:buffer integer range 0 to 59
	);
end entity counter;
	
architecture behavior of counter is
begin
	process(clk,reset)
	begin
		if(reset='1') then
			num<=0;
		elsif (clk 'event and clk='1') then
			if(hold='1') then
				num<=num;
				else if(num=59) then
					num<=0;
				else
					num<=num+1;
				end if;
			end if;
		end if;
	end process;
end behavior;

library ieee;
use ieee.std_logic_1164.all;
entity fenwei is
	port(numin:in integer range 0 to 30;
	     numa,numb:out integer range 0 to 9
	);
end entity fenwei;

architecture behavior of fenwei is
begin
	process(numin)
	begin
		if(numin>=30)then
			numa<=3;
			numb<=numin-30;
		elsif(numin>=20) then
			numa<=2;
			numb<=numin-20;
		elsif(numin>=10) then
			numa<=1;
			numb<=numin-10;
		else
			numa<=0;
			numb<=numin;
		end if;
	end process;
end behavior;

三人表决器