Verilog语法练习：HDL Bits做题笔记（1）

目录

前言

一、Getting Started

1.1：Step one

Problem Statement:

Solution:

1.2、Zero

Problem Statement:

Solution:

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前言

为了更好的掌握Verilog 语法知识，加深对相关知识点的理解，为此做了HDL Bits上的题目，并在此做笔记，方便日后回顾，查漏补缺。

一、Getting Started

1.1：Step one

Problem Statement:

We're going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here's the description of the circuit you need to build for this exercise:

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

Solution:

module top_module( output one );

// Insert your code here
    assign one=1;

endmodule

1.2、Zero

Problem Statement:

Build a circuit with no inputs and one output that outputs a constant 0

Solution:

module top_module(
    output zero
);// Module body starts after semicolon
 assign zero=1'b0;
endmodule