HDLbits---Verilog Language---Procedures

1.Always block1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
assign out_assign=a&b;
    always@(*)begin
       out_alwaysblock<=a&b;
    end
endmodule

2.Always blocks2

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
assign out_assign=a^b;
    always@(*)begin
        out_always_comb=a^b;
    end
    always@(posedge clk) begin
        out_always_ff=a^b;
    end
endmodule

3.alwaysif

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign=(sel_b1&&sel_b2&&b)||(sel_b1&&~sel_b2&&a)||(~sel_b1&&~sel_b2&&a)||(~sel_b1&&sel_b2&&a);
    wire[1:0] d;
    assign d={sel_b2,sel_b1};
    always@(*) begin
        if(d==2'b11) begin
            out_always=b; end
        else begin
            out_always=a; end
    end
    
endmodule

4.always if2

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
             keep_driving =0;
    end

endmodule

5.aleays_case

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            0:out<=data0;
            1:out<=data1;
            2:out<=data2;
            3:out<=data3;
            4:out<=data4;
            5:out<=data5;  
            default:
                out=0;
        endcase
    end
   

endmodule

6.always_case2

module top_module (
    input      [3:0]  in,
    output reg [1:0]  pos  
);
 
always @(*) begin
    case(in)
        4'b0000: pos = 0;
        4'b0001: pos = 0;
        4'b0010: pos = 1;
        4'b0100: pos = 2;
        4'b1000: pos = 3;
        4'b0011: pos = 0;
        4'b0110: pos = 1;
        4'b1100: pos = 2;
        4'b0101: pos = 0;
        4'b1010: pos = 1;
        4'b1001: pos = 0;
        4'b0111: pos = 0;
        4'b1110: pos = 1;
        4'b1011: pos = 0;
        4'b1101: pos = 0;
        4'b1111: pos = 0;
    endcase
end
 
endmodule

7.always_casez

module top_module (
    input      [7:0]  in,
    output reg [2:0]  pos  
);
 
always @(*) begin
    casez(in)
        8'bzzzzzzz1: pos = 0;   //z表示不在乎这个是什么值。只需要满足后面位的情况
        8'bzzzzzz10: pos = 1;
        8'bzzzzz100: pos = 2;
        8'bzzzz1000: pos = 3;
        8'bzzz10000: pos = 4;
        8'bzz100000: pos = 5;
        8'bz1000000: pos = 6;
        8'b10000000: pos = 7;
    endcase
end
 
endmodule

8.always_nolatches

module top_module (
    input [15:0]  scancode,
    output reg    left,
    output reg    down,
    output reg    right,
    output reg    up  
); 
 
always @(*) begin
    up    = 1'b0;
    down  = 1'b0;
    left  = 1'b0;
    right = 1'b0;
    case(scancode)
        16'he075: up    = 1'b1;
        16'he072: down  = 1'b1;
        16'he06b: left  = 1'b1;
        16'he074: right = 1'b1;
        default: begin
                  up    = 1'b0;
                  down  = 1'b0;
                  left  = 1'b0;
                  right = 1'b0;
        end    
    endcase
end
 
endmodule