【FPGA】Vivado综合停滞、死机（PID Not Specified）解决方法

在学FPGA的过程中发现：

Vivado一点run synthesis就挂死，原来还以为只是综合时间比较长，但等了30分钟还是没有综合完成。并且不管多简单的工程都结果都一样。

仔细查看了vivado的log，发现Message里面有个Problem encountered：PID not specified.

后面就没有其它信息了，问题应该出现在这里了，压根综合没跑起来。

看log也发现后续没跑起来：

start_gui
open_project E:/projec/run_led/run_led.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 6
[Fri Aug 27 23:55:51 2021] Launched synth_1...
Run output will be captured here: E:/projec/run_led/run_led.runs/synth_1/runme.log

考虑到是不是Vivado的某个工具被360拦截了，把360关了再跑，还是不行。

考虑到是不是安装Vivado的时候没关闭360，导致某个安装过程被拦截了？

于是先把vivado卸载了，再关闭360，再重新安装Vivado。果然，可以正常综合了。

start_gui
open_project E:/projec/run_led/run_led.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 6
[Fri Aug 27 23:55:51 2021] Launched synth_1...
Run output will be captured here: E:/projec/run_led/run_led.runs/synth_1/runme.log


open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7z035ffg676-2
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7z035ffg676-2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1059.699 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transforme