MCU软核 1. Altera FPGA上运行8051


0. 环境

- Quartus 13
- EP4CE6E22开发板
- keil c51 
- ag10kl144h(本工程兼容AGM)

下载8051源码:https://www.oreganosystems.at/products/ip-cores/8051-ip-core

1. Create Project

File --> New Project Wizard

位置:E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello
名字:mc8051_hello

next - next
选择芯片
EP4CE6E22C6

Simulation     None     None


2. 添加源码


2.1 顶层文件


mc8051顶层文件样例请参考 mc8051_hello.v

module mc8051_hello(
	input 	Clk50M,		//板级时钟源,50M
	input 	Rst_n,    	//复位端口
	input 	int0_i,   	//mc8051外部中断0输入
	input 	int1_i,   	//mc8051外部中断1输入
	input 	all_t0_i, 	//mc8051计数器0输入
	input 	all_t1_i, 	//mc8051计数器1输入 

	input 	[7:0]p0_i,  //mc8051端口0输入 
	input 	[7:0]p1_i,  //mc8051端口1输入 
	input 	[7:0]p2_i,  //mc8051端口2输入 
	input 	[7:0]p3_i,  //mc8051端口3输入 

	output 	[7:0]p0_o,  //mc8051端口0输出      
	output 	[7:0]p1_o,  //mc8051端口1输出      
	output 	[7:0]p2_o,  //mc8051端口2输出      
	output 	[7:0]p3_o,  //mc8051端口3输出

	input 	all_rxd_i, 	//mc8051串口接收端口     
	output 	all_rxd_o,  //mc8051串口方式0时输出端口
	output 	all_txd_o,  //mc8051串口发送端口 
	output 	all_rxdwr_o //rxd 输入/输出方向控制信号(高电平输出)
);

wire Clk18M;

//例化PLL模块   
pll pll(
	.inclk0(Clk50M),
	.c0(Clk18M)
);

//例化mc8051核   
mc8051_top mc8051_top_inst(
	.clk(Clk18M),       
	//.reset(~Rst_n), //mc8051为高电平复位,因此将复位按键状态取反接到reset上
	.reset(0),
	.int0_i(int0_i),
	.int1_i(int1_i),
	.all_t0_i(all_t0_i),
	.all_t1_i(all_t1_i),  

	.p0_i(p0_i),      
	.p1_i(p1_i),     
	.p2_i(p2_i),      
	.p3_i(p3_i),      

	.p0_o(p0_o),      
	.p1_o(p1_o),      
	.p2_o(p2_o),      
	.p3_o(p3_o),

	.all_rxd_i(all_rxd_i),      
	.all_rxd_o(all_rxd_o),
	.all_txd_o(all_txd_o),
	.all_rxdwr_o(all_rxdwr_o)
);

endmodule

2.2 ROM


创建一个ROM模块所需使用的初始化文件
File -> New -> Memory Files -> Hexadecimal (Intel-Format)File
-> Number of words:        4096
-> Word size:            8
File -> save as ... -> E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/rtl/mc8051_hello.hex

MCU软核 1. Altera FPGA上运行8051_第1张图片

MCU软核 1. Altera FPGA上运行8051_第2张图片

2.3 生成ROM模块

注意这部分的hex文件需要完成keil部分章节才会生成。
Tools -> MegaWizard Plug-In Manager… -> Create a new custom megafunction variation -> Next ->ROM: 1-PORT -> 语言选择VHDL
-> 地址:E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/rtl/altera_ip/mc8051_rom -> Next
-> how wide: 8 bits -> how many: 4096
-> 取消勾选 'q' output port
-> file name: E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/keil/mc8051_hello/Objects/mc8051_hello.hex
-> 勾选Allow In-System Memory Content Editor to capture and update content independently of the system clock
-> The Instance ID of this ROM is: ROM0
-> 勾选 mc8051_rom.cmp 和 mc8051_rom_inst.vhd

MCU软核 1. Altera FPGA上运行8051_第3张图片

MCU软核 1. Altera FPGA上运行8051_第4张图片

MCU软核 1. Altera FPGA上运行8051_第5张图片

2.4 生成RAM模块


Tools -> MegaWizard Plug-In Manager… -> Create a new custom megafunction variation -> Next ->RAM: 1-PORT -> 语言选择VHDL
-> 地址:E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/rtl/altera_ip/mc8051_ram -> Next
-> how wide: 8 bits -> how many: 128
-> 取消勾选 'q' output port
-> 勾选 Create one clock enable signal for each clock signal.(clken)
-> 勾选 mc8051_ram.cmp 和 mc8051_ram_inst.vhd

MCU软核 1. Altera FPGA上运行8051_第6张图片

MCU软核 1. Altera FPGA上运行8051_第7张图片MCU软核 1. Altera FPGA上运行8051_第8张图片MCU软核 1. Altera FPGA上运行8051_第9张图片 MCU软核 1. Altera FPGA上运行8051_第10张图片

Tools -> MegaWizard Plug-In Manager… -> Create a new custom megafunction variation -> Next ->RAM: 1-PORT -> 语言选择VHDL
-> 地址:E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/rtl/altera_ip/mc8051_ramx -> Next
-> how wide: 8 bits -> how many: 2048
-> 取消勾选 'q' output port
-> 勾选 mc8051_ramx.cmp 和 mc8051_ramx_inst.vhd

MCU软核 1. Altera FPGA上运行8051_第11张图片

MCU软核 1. Altera FPGA上运行8051_第12张图片 

MCU软核 1. Altera FPGA上运行8051_第13张图片 

MCU软核 1. Altera FPGA上运行8051_第14张图片 

2.5 mc8051_core


mc8051_design_v1.6\Version1_6\vhdl
拷贝到
E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello\rtl\mc8051core打开 mc8051_p.vhd 文件

--------------------------------------------------------------------
  -- START: Component declarations for simulation models
  --------------------------------------------------------------------
  component mc8051_ram
    port (
        clk        : in  std_logic;
        reset      : in  std_logic;
        ram_data_i : in  std_logic_vector(7 downto 0);
        ram_data_o : out std_logic_vector(7 downto 0);
        ram_adr_i  : in  std_logic_vector(6 downto 0);
        ram_wr_i   : in  std_logic;
        ram_en_i   : in  std_logic);
  end component;

  component mc8051_ramx
    port (
        clk        : in  std_logic;
        reset      : in  std_logic;
        ram_data_i : in  std_logic_vector(7 downto 0);
        ram_data_o : out std_logic_vector(7 downto 0);
        ram_adr_i  : in  std_logic_vector(15 downto 0);
        ram_wr_i   : in  std_logic);
  end component;

  component mc8051_rom
    port (
        clk        : in  std_logic;
        reset      : in  std_logic;
        rom_data_o : out std_logic_vector(7 downto 0); 
        rom_adr_i  : in  std_logic_vector(15 downto 0)); 
  end component;
  --------------------------------------------------------------------
  -- END: Component declarations for simulation models
  --------------------------------------------------------------------


  
替换为

--------------------------------------------------------------------
  -- START: Component declarations for simulation models
  --------------------------------------------------------------------
    component mc8051_ram 
    port ( 
        clock   : in  std_logic;      
        data    : in  std_logic_vector(7 downto 0);            
        q       : out std_logic_vector(7 downto 0);            
        address : in  std_logic_vector(6 downto 0);            
        wren    : in  std_logic;            
        clken   : in  std_logic);   
    end component; 

    component mc8051_ramx     
    port ( 
        clock   : in  std_logic;      
        data    : in  std_logic_vector(7 downto 0);            
        q       : out std_logic_vector(7 downto 0);            
        address : in  std_logic_vector(10 downto 0);            
        wren    : in  std_logic);   
    end component;
    
    component mc8051_rom     
    port ( 
        clock   : in  std_logic; 
        q       : out std_logic_vector(7 downto 0);  
        address : in  std_logic_vector(11 downto 0));   
    end component;

  --------------------------------------------------------------------
  -- END: Component declarations for simulation models
  --------------------------------------------------------------------


打开 mc8051_top_struc.vhd 文件
添加

  signal s_rom_adr_sml:   std_logic_vector(11 downto 0);  -- new
  signal s_ramx_adr_sml:   std_logic_vector(10 downto 0);  -- new


添加

    s_rom_adr_sml <= std_logic_vector(s_rom_adr(11 downto 0));  -- *** new    
    s_ramx_adr_sml <= std_logic_vector(s_ramx_adr(10 downto 0));  -- *** new  

MCU软核 1. Altera FPGA上运行8051_第15张图片
再修改

--------------------------------------------------------------------
  -- Hook up the general purpose 128x8 synchronous on-chip RAM. 
  i_mc8051_ram : mc8051_ram     
    port map ( 
        clock       => clk, 
        data        => s_ram_data_in,     
        q           => s_ram_data_out, 
        address     => s_ram_adr,
        wren        => s_ram_wr,
        clken       => s_ram_en);

  -- THIS RAM IS A MUST HAVE!!
  --------------------------------------------------------------------


  --------------------------------------------------------------------
  -- Hook up the (up to) 64kx8 synchronous on-chip ROM.
    i_mc8051_rom : mc8051_rom
        port map (
            clock   => clk,
            q       => s_rom_data,
            address => s_rom_adr_sml);
  -- THE ROM OF COURSE IS A MUST HAVE, ALTHOUGH THE SIZE CAN BE SMALLER!!
  --------------------------------------------------------------------
  
    
  --------------------------------------------------------------------
  -- Hook up the (up to) 64kx8 synchronous RAM.
    i_mc8051_ramx : mc8051_ramx
        port map ( 
            clock   => clk,
            data    => s_ramx_data_out,
            q       => s_ramx_data_in,
            address => s_ramx_adr_sml,
            wren    => s_ramx_wr);
  -- THIS RAM (IF USED) CAN BE ON OR OFF CHIP, THE SIZE IS ARBITRARY.
  --------------------------------------------------------------------


  
添加mc8051 Core相关文件到Quartus II工程中
对部分文件的文件名进行更改。原版的VHDL源码,部分文件的文件名末尾加了有“_”,而实际源码中的模块名没有加“_”,因此,如果将这些文件直接添加到Quartus II工程中,编译就会报错。
名字带CFG的文件不需要添加。

2.6 pll


Tools -> MegaWizard Plug-In Manager… -> Create a new custom megafunction variation -> Next ->ALTPLL -> 语言选择verilog hdl
-> 地址:E:/Workspaces/Quartus/EP4CE6_Core/mc8051_hello/rtl/altera_ip/pll -> Next
-> inclk0: 50MHz
-> 取消勾选Create an 'areset' input to asynchronously reset the PLL
-> 取消勾选Create 'locked' output
-> c0 output clock frequency: 18MHz

MCU软核 1. Altera FPGA上运行8051_第16张图片

MCU软核 1. Altera FPGA上运行8051_第17张图片

MCU软核 1. Altera FPGA上运行8051_第18张图片

2.7 设置工程顶层文件

在Files栏中,选中mc8051_top.vhd文件,点击右键,选择“Set as Top-Level Entity”,即可将mc8051_top.vhd设置为工程的顶层文件,(这里设置为顶层主要是为了封装IP核方便,临时性的,并不是最终作为工程顶层)。如图 2.23 所示:

3. 编译 

MCU软核 1. Altera FPGA上运行8051_第19张图片

4. 配置引脚


打开 mc8051_hello.qsf
添加

set_location_assignment PIN_23 -to Clk50M
set_location_assignment PIN_88 -to Rst_n        # 掌中宝1A 复位按钮
set_location_assignment PIN_87 -to p1_o[1]        # 掌中宝1A led2
set_location_assignment PIN_98 -to p1_o[0]        # 掌中宝1A led1
# set_location_assignment PIN_42 -to p1_o[0]        # zhybcjbk_v011 led1
# set_location_assignment PIN_129 -to p1_o[1]        # zhybcjbk_v011 led2

编辑完后再次编译工程。 

5. keil

创建工程
Project -> New uVision Project -> E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello\keil\mc8051_hello
-> at89c51

添加源码
E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello\keil\mc8051_hello\src\main.c

设置生成Hex 
右键Target 1 -> Options for Target 'Target 1' -> Output -> 勾选Create HEX File

MCU软核 1. Altera FPGA上运行8051_第20张图片

6. 验证与下载

重新编译再下载 sof

在Quartus中点击
Assignments—— Device——Device and Pin Options——Unused Pins
As input tri-stated

Assignments—— Device——Device and Pin Options——Dual-Purpose Pins
全部选择Use as regual I/O

Assignments—— Device——Device and Pin Options——Voltage
3.3-V LVTTL


6.1 FPGA程序

Open programmer --> 
add file --> output_files/add_sub_ip_test.sof

Hardware Setup:        USB-Blaster
Mode:                JTAG

MCU软核 1. Altera FPGA上运行8051_第21张图片 

6.2 FPGA程序-固化

File -> Convert Programming Files
    -> Programming file type -> JTAG Indirect Configuration File(.jic)
    -> Configuration device -> EPCS16
    -> File name -> output_files/mc8051_hello.jic
    -> Flash Loader -> Add Device -> EP4CE6
    -> SOF Data -> Add File -> mc8051_hello.sof
    -> Generate

MCU软核 1. Altera FPGA上运行8051_第22张图片 

打开Programmer,选择jlc文件,mc8051_hello.sof
勾选 output_files/mc8051_hello.sof 一行的Program/Configure

6.3 ROM

MCU软核 1. Altera FPGA上运行8051_第23张图片 

Tools -> In-System Memory Content Editor -> Hardware Setup: USB-Blaster
ROM0 -> 右键ROM0 -> Import Data From File -> E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello\keil\mc8051_hello\Objects\mc8051_hello.hex
-> Write Data to In-System Memory

但是这个ROM是在8051的IP核的,不是外部硬件ROM,因此掉电就要重新下载了。

7. Supre

这部分将EP4CE6工程转换为AGM工程。

D:\Supra-2023.02.b0-7773ca8a-win64-all\bin\Supra.exe

创建工程
Project -> New Project -> 
project directory:    E:\Workspaces\Supra\zhybcjbk\mc8051_hello
project name:        mc8051_hello

工程migrate
Tools -> Migrate
select migrate from directory:    E:\Workspaces\Quartus\EP4CE6_Core\mc8051_hello
input design name:                mc8051_hello
Select device:                    AG10KL144H
按Next转换

quartus
打开 E:\Workspaces\Supra\zhybcjbk\mc8051_hello\mc8051_hello.qpf

Tools -> TCL Scripts 
选择 af_quartus.td,点击Run

Supre编译工程
回到Supre界面,点击 Next -> Finish -> 稍后会弹出窗口提示Compile deisgn watch done.

文件说明
_SRAM.prg 文件为片内 SRAM 写入,通过 JTAG 烧写,掉电即失效,可用于设计调试;
_master.prg 文件为 Master(AS)配置方式下,通过 JTAG 烧写外部配置 FLASH的文件;
_master.bin 为 Master(AS)配置方式下,配置 Flash 的标准烧写文件;
_master_as.prg 调用此 bin 文件,通过 AS 口直接烧写 FLASH;
.bin 为基本配置文件,可用来产生其它类型烧写文件,也可用于 Slave(PS)配置方式;rbf 文件为此 bin 文件的字节高低位反向的转换后文件。

参考:1. mc8051源码下载,https://www.oreganosystems.at/products/ip-cores/8051-ip-core
2. FPGA配置MC8051IP软核,https://blog.csdn.net/QuanSirX/article/details/105143773
3. 【小梅哥FPGA进阶教程】MC8051软核在FPGA上的使用,https://www.cnblogs.com/xiaomeige/p/6403094.html


 

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