Quartus Ⅱ中遇到的问题

记录Quartus中遇到的报错

一、Failed to launch MegaWizard Plug-In Manager

报错：Failed to launch MegaWizard Plug-In Manager. PLL IntelFPGA IP v18.1 could not be found in the specified librarypaths.

原因：编译后无法再打开IP核查看了，因为为Inter收购Altera后一些名称的改动没改好

解决方法一：找到Quartus安装路径D:\intelFPGA\18.1\ip\altera\altera_pll\pll_wizard.plt，用文本编辑器打开
 

[Basic Functions|Clocks; PLLs and Resets|PLL]
Altera PLL v18.1= "%t" "%w/../common/lib/megawizard.pl" --wizard:altera_pll  --early_gen:on --wizard_file:"%w/source/top/pll_hw.tcl" --familyparameter:device_family %f %o %h



 


Altera PLL
Altera PLL v10.0
Altera PLL v10.1
Altera PLL v11.0
Altera PLL v11.1
Altera PLL v12.0
Altera PLL v12.1
Altera PLL v13.0
Altera PLL v13.1
Altera PLL v14.0
Altera PLL v14.1
Altera PLL v15.0
Altera PLL v15.1
Altera PLL v16.0
Altera PLL v16.1
Altera PLL v17.0
Altera PLL v17.1
Altera PLL v18.0
Altera PLL v18.1
Altera PLL v19.0
Altera PLL v19.1
Altera PLL v20.0
Altera PLL v20.1

将后的Altra PLL修改成PLL Intel FPGA，对应自己的版本即可

[Basic Functions|Clocks; PLLs and Resets|PLL]
Altera PLL v18.1= "%t" "%w/../common/lib/megawizard.pl" --wizard:altera_pll  --early_gen:on --wizard_file:"%w/source/top/pll_hw.tcl" --familyparameter:device_family %f %o %h



 


Altera PLL
Altera PLL v10.0
Altera PLL v10.1
Altera PLL v11.0
Altera PLL v11.1
Altera PLL v12.0
Altera PLL v12.1
Altera PLL v13.0
Altera PLL v13.1
Altera PLL v14.0
Altera PLL v14.1
Altera PLL v15.0
Altera PLL v15.1
Altera PLL v16.0
Altera PLL v16.1
Altera PLL v17.0
Altera PLL v17.1
Altera PLL v18.0
PLL Intel FPGA v18.1
Altera PLL v19.0
Altera PLL v19.1
Altera PLL v20.0
Altera PLL v20.1

解决方法二：在PLL.qip->PLL.v的第一行的注释，将PLL Intel FPGA vXX.X改成Altera PLL vXX.X

二、 quartus调用IP核无法生成.vo文件

问题：在Quartus中调用IP核后无法生成.vo文件，导致modelsim报错

解决方法：在Quartus的Assignments->Settings->EDA Tool Settings中，勾选Run gate-level simulation automatically after compilation，再重新编译即可

用上面解决办法后每次编译完就会进行modelsim仿真，可以仿真完成后再取消勾选