ov5640帧率配置_FPGA配置OV5640摄像头及RGB图像数据采集

1 `timescale 1ns /1ps2

3

4 modulereg_config(5 inputclk,6 inputrst_n,7

8 inputen,9 outputfinish,10

11 inoutsio_d,12 outputsio_c13 );14

15 localparam WR_ID = 8'h78;

16 localparam RW_CTRL = 2'b11;//读

17 wiresio_out_en;18 wiresio_out;19 wiresio_in;20 reg [9-1:0] reg_cnt;21 wireadd_reg_cnt,end_reg_cnt;22 regconfig_flag;23 reg [26-1:0] op_reg_data;24 wirerdy;25 regwr_en;26 reg [16-1:0] reg_addr;27 reg [8-1:0] wr_data;28 regconfig_done;29 reg [ (2-1):0] rw_cnt ;30 wireadd_rw_cnt ;31 wireend_rw_cnt ;32 regrd_en;33 (*DONT_TOUCH = "TRUE"*)wire [8-1:0] rd_data;34 (*DONT_TOUCH = "TRUE"*)wirerd_vld;35

36 sccb_interface sccb_interface(37 .clk (clk) ,38 .rst_n (rst_n) ,39 .wr_en (wr_en) ,40 .rd_en (rd_en),41 .id_addr (WR_ID) ,42 .reg_addr (reg_addr) ,43 .wr_data (wr_data) ,44 .rd_data (rd_data),45 .rd_vld (rd_vld),46 .rdy (rdy) ,47 .sio_c (sio_c) ,48 .sio_out_en(sio_out_en) ,49 .sio_out (sio_out) ,50 .sio_in (sio_in)51 );52

53 assign sio_d = sio_out_en ? sio_out : 1'bz;

54 assign sio_in =sio_d;55

56 always @(posedge clk or negedge rst_n) begin

57 if (rst_n==0) begin

58 rw_cnt <= 0;59 end

60 else if(add_rw_cnt) begin

61 if(end_rw_cnt)62 rw_cnt <= 0;63 else

64 rw_cnt <= rw_cnt+1;65 end

66 end

67 assign add_rw_cnt = (config_flag &&rdy);68 assign end_rw_cnt = add_rw_cnt && rw_cnt == (2)-1 ;//0 write 1 read

69

70 always @(posedge clk or negedge rst_n)begin

71 if(!rst_n)begin

72 reg_cnt <= 0;73 end

74 else if(add_reg_cnt)begin

75 if(end_reg_cnt)76 reg_cnt <= 0;77 else

78 reg_cnt <= reg_cnt + 1;79 end

80 end

81

82 assign add_reg_cnt =end_rw_cnt;83 assign end_reg_cnt = add_reg_cnt && reg_cnt == 261-1;84

85 //配置指令

86 always @(posedge clk or negedge rst_n)begin

87 if(rst_n==1'b0)begin

88 wr_en <= 0;89 reg_addr <= 0;90 wr_data <= 0;91 end

92 else if(add_rw_cnt && rw_cnt == 0)begin

93 wr_en <= op_reg_data[25];94 reg_addr <= op_reg_data[23:8];95 wr_data <= op_reg_data[7:0];96 end

97 else if(end_rw_cnt)begin

98 rd_en <= op_reg_data[24];99 reg_addr <= op_reg_data[23:8];100 end

101 else begin

102 wr_en <= 0;103 rd_en <= 0;104 end

105 end

106

107

108 always @(posedge clk or negedge rst_n)begin

109 if(rst_n==1'b0)begin

110 config_flag <= 0;111 end

112 else if(en && !config_flag && !config_done)begin

113 config_flag <= 1;114 end

115 else if(end_reg_cnt)116 config_flag <= 0;117 end

118

119 always @(posedge clk or negedge rst_n)begin

120 if(rst_n==1'b0)begin

121 config_done <= 0;122 end

123 else if(end_reg_cnt)begin

124 config_done <= 1;125 end

126 end

127

128 assign finish = config_done &&rdy;129

130 always@(*)131 begin//op_reg_data [25] wr [24] rd [23:8] reg_addr [7:0] wr_data

132 case(reg_cnt)133 //15fps VGA YUV output//24MHz input clock, 24MHz PCLK

134 0:op_reg_data= {RW_CTRL, 24'h310311};// system clock from pad, bit[1]

135 1:op_reg_data= {RW_CTRL, 24'h300882};// software reset, bit[7]// delay 5ms

136 2:op_reg_data= {RW_CTRL, 24'h300842};// software power down, bit[6]

137 3:op_reg_data= {RW_CTRL, 24'h310303};// system clock from PLL, bit[1]

138 4:op_reg_data= {RW_CTRL, 24'h3017ff};// FREX, Vsync, HREF, PCLK, D[9:6] output enable

139 5:op_reg_data= {RW_CTRL, 24'h3018ff};// D[5:0], GPIO[1:0] output enable

140 6:op_reg_data= {RW_CTRL, 24'h30341A};// MIPI 10-bit

141 7:op_reg_data= {RW_CTRL, 24'h303713};// PLL root divider, bit[4], PLL pre-divider, bit[3:0]

142 8:op_reg_data= {RW_CTRL, 24'h310801};// PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] // SCLK root divider, bit[1:0]

143 9:op_reg_data= {RW_CTRL, 24'h363036};

144 10:op_reg_data= {RW_CTRL, 24'h36310e};

145 11:op_reg_data= {RW_CTRL, 24'h3632e2};

146 12:op_reg_data= {RW_CTRL, 24'h363312};

147 13:op_reg_data= {RW_CTRL, 24'h3621e0};

148 14:op_reg_data= {RW_CTRL, 24'h3704a0};

149 15:op_reg_data= {RW_CTRL, 24'h37035a};

150 16:op_reg_data= {RW_CTRL, 24'h371578};

151 17:op_reg_data= {RW_CTRL, 24'h371701};

152 18:op_reg_data= {RW_CTRL, 24'h370b60};

153 19:op_reg_data= {RW_CTRL, 24'h37051a};

154 20:op_reg_data= {RW_CTRL, 24'h390502};

155 21:op_reg_data= {RW_CTRL, 24'h390610};

156 22:op_reg_data= {RW_CTRL, 24'h39010a};

157 23:op_reg_data= {RW_CTRL, 24'h373112};

158 24:op_reg_data= {RW_CTRL, 24'h360008};// VCM control

159 25:op_reg_data= {RW_CTRL, 24'h360133};// VCM control

160 26:op_reg_data= {RW_CTRL, 24'h302d60};// system control

161 27:op_reg_data= {RW_CTRL, 24'h362052};

162 28:op_reg_data= {RW_CTRL, 24'h371b20};

163 29:op_reg_data= {RW_CTRL, 24'h471c50};

164 30:op_reg_data= {RW_CTRL, 24'h3a1343};// pre-gain = 1.047x

165 31:op_reg_data= {RW_CTRL, 24'h3a1800};// gain ceiling

166 32:op_reg_data= {RW_CTRL, 24'h3a19f8};// gain ceiling = 15.5x

167 33:op_reg_data= {RW_CTRL, 24'h363513};

168 34:op_reg_data= {RW_CTRL, 24'h363603};

169 35:op_reg_data= {RW_CTRL, 24'h363440};

170 36:op_reg_data= {RW_CTRL, 24'h362201}; // 50/60Hz detection 50/60Hz 灯光条纹过滤

171 37:op_reg_data= {RW_CTRL, 24'h3c0134};// Band auto, bit[7]

172 38:op_reg_data= {RW_CTRL, 24'h3c0428};// threshold low sum

173 39:op_reg_data= {RW_CTRL, 24'h3c0598};// threshold high sum

174 40:op_reg_data= {RW_CTRL, 24'h3c0600};// light meter 1 threshold[15:8]

175 41:op_reg_data= {RW_CTRL, 24'h3c0708};// light meter 1 threshold[7:0]

176 42:op_reg_data= {RW_CTRL, 24'h3c0800};// light meter 2 threshold[15:8]

177 43:op_reg_data= {RW_CTRL, 24'h3c091c};// light meter 2 threshold[7:0]

178 44:op_reg_data= {RW_CTRL, 24'h3c0a9c};// sample number[15:8]

179 45:op_reg_data= {RW_CTRL, 24'h3c0b40};// sample number[7:0]

180 46:op_reg_data= {RW_CTRL, 24'h381000};// Timing Hoffset[11:8]

181 47:op_reg_data= {RW_CTRL, 24'h381110};// Timing Hoffset[7:0]

182 48:op_reg_data= {RW_CTRL, 24'h381200};// Timing Voffset[10:8]

183 49:op_reg_data= {RW_CTRL, 24'h370864};

184 50:op_reg_data= {RW_CTRL, 24'h400102};// BLC start from line 2

185 51:op_reg_data= {RW_CTRL, 24'h40051a};// BLC always update

186 52:op_reg_data= {RW_CTRL, 24'h300000};// enable blocks

187 53:op_reg_data= {RW_CTRL, 24'h3004ff};// enable clocks

188 54:op_reg_data= {RW_CTRL, 24'h300e58};// MIPI power down, DVP enable

189 55:op_reg_data= {RW_CTRL, 24'h302e00};

190 56:op_reg_data= {RW_CTRL, 24'h430060};// RGB565

191 57:op_reg_data= {RW_CTRL, 24'h501f01};// ISP RGB

192 58:op_reg_data= {RW_CTRL, 24'h440e00};

193 59:op_reg_data= {RW_CTRL, 24'h5000a7}; // Lenc on, raw gamma on, BPC on, WPC on, CIP on // AEC target 自动曝光控制

194 60:op_reg_data= {RW_CTRL, 24'h3a0f30};// stable range in high

195 61:op_reg_data= {RW_CTRL, 24'h3a1028};// stable range in low

196 62:op_reg_data= {RW_CTRL, 24'h3a1b30};// stable range out high

197 63:op_reg_data= {RW_CTRL, 24'h3a1e26};// stable range out low

198 64:op_reg_data= {RW_CTRL, 24'h3a1160};// fast zone high

199 65:op_reg_data= {RW_CTRL, 24'h3a1f14};// fast zone low// Lens correction for ? 镜头补偿

200 66:op_reg_data= {RW_CTRL, 24'h580023};

201 67:op_reg_data= {RW_CTRL, 24'h580114};

202 68:op_reg_data= {RW_CTRL, 24'h58020f};

203 69:op_reg_data= {RW_CTRL, 24'h58030f};

204 70:op_reg_data= {RW_CTRL, 24'h580412};

205 71:op_reg_data= {RW_CTRL, 24'h580526};

206 72:op_reg_data= {RW_CTRL, 24'h58060c};

207 73:op_reg_data= {RW_CTRL, 24'h580708};

208 74:op_reg_data= {RW_CTRL, 24'h580805};

209 75:op_reg_data= {RW_CTRL, 24'h580905};

210 76:op_reg_data= {RW_CTRL, 24'h580a08};

211 77:op_reg_data= {RW_CTRL, 24'h580b0d};

212 78:op_reg_data= {RW_CTRL, 24'h580c08};

213 79:op_reg_data= {RW_CTRL, 24'h580d03};

214 80:op_reg_data= {RW_CTRL, 24'h580e00};

215 81:op_reg_data= {RW_CTRL, 24'h580f00};

216 82:op_reg_data= {RW_CTRL, 24'h581003};

217 83:op_reg_data= {RW_CTRL, 24'h581109};

218 84:op_reg_data= {RW_CTRL, 24'h581207};

219 85:op_reg_data= {RW_CTRL, 24'h581303};

220 86:op_reg_data= {RW_CTRL, 24'h581400};

221 87:op_reg_data= {RW_CTRL, 24'h581501};

222 88:op_reg_data= {RW_CTRL, 24'h581603};

223 89:op_reg_data= {RW_CTRL, 24'h581708};

224 90:op_reg_data= {RW_CTRL, 24'h58180d};

225 91:op_reg_data= {RW_CTRL, 24'h581908};

226 92:op_reg_data= {RW_CTRL, 24'h581a05};

227 93:op_reg_data= {RW_CTRL, 24'h581b06};

228 94:op_reg_data= {RW_CTRL, 24'h581c08};

229 95:op_reg_data= {RW_CTRL, 24'h581d0e};

230 96:op_reg_data= {RW_CTRL, 24'h581e29};

231 97:op_reg_data= {RW_CTRL, 24'h581f17};

232 98:op_reg_data= {RW_CTRL, 24'h582011};

233 99:op_reg_data= {RW_CTRL, 24'h582111};

234 100:op_reg_data= {RW_CTRL, 24'h582215};

235 101:op_reg_data= {RW_CTRL, 24'h582328};

236 102:op_reg_data= {RW_CTRL, 24'h582446};

237 103:op_reg_data= {RW_CTRL, 24'h582526};

238 104:op_reg_data= {RW_CTRL, 24'h582608};

239 105:op_reg_data= {RW_CTRL, 24'h582726};

240 106:op_reg_data= {RW_CTRL, 24'h582864};

241 107:op_reg_data= {RW_CTRL, 24'h582926};

242 108:op_reg_data= {RW_CTRL, 24'h582a24};

243 109:op_reg_data= {RW_CTRL, 24'h582b22};

244 110:op_reg_data= {RW_CTRL, 24'h582c24};

245 111:op_reg_data= {RW_CTRL, 24'h582d24};

246 112:op_reg_data= {RW_CTRL, 24'h582e06};

247 113:op_reg_data= {RW_CTRL, 24'h582f22};

248 114:op_reg_data= {RW_CTRL, 24'h583040};

249 115:op_reg_data= {RW_CTRL, 24'h583142};

250 116:op_reg_data= {RW_CTRL, 24'h583224};

251 117:op_reg_data= {RW_CTRL, 24'h583326};

252 118:op_reg_data= {RW_CTRL, 24'h583424};

253 119:op_reg_data= {RW_CTRL, 24'h583522};

254 120:op_reg_data= {RW_CTRL, 24'h583622};

255 121:op_reg_data= {RW_CTRL, 24'h583726};

256 122:op_reg_data= {RW_CTRL, 24'h583844};

257 123:op_reg_data= {RW_CTRL, 24'h583924};

258 124:op_reg_data= {RW_CTRL, 24'h583a26};

259 125:op_reg_data= {RW_CTRL, 24'h583b28};

260 126:op_reg_data= {RW_CTRL, 24'h583c42};

261 127:op_reg_data= {RW_CTRL, 24'h583dce};// lenc BR offset // AWB 自动白平衡

262 128:op_reg_data= {RW_CTRL, 24'h5180ff};// AWB B block

263 129:op_reg_data= {RW_CTRL, 24'h5181f2};// AWB control

264 130:op_reg_data= {RW_CTRL, 24'h518200};// [7:4] max local counter, [3:0] max fast counter

265 131:op_reg_data= {RW_CTRL, 24'h518314};// AWB advanced

266 132:op_reg_data= {RW_CTRL, 24'h518425};

267 133:op_reg_data= {RW_CTRL, 24'h518524};

268 134:op_reg_data= {RW_CTRL, 24'h518609};

269 135:op_reg_data= {RW_CTRL, 24'h518709};

270 136:op_reg_data= {RW_CTRL, 24'h518809};

271 137:op_reg_data= {RW_CTRL, 24'h518975};

272 138:op_reg_data= {RW_CTRL, 24'h518a54};

273 139:op_reg_data= {RW_CTRL, 24'h518be0};

274 140:op_reg_data= {RW_CTRL, 24'h518cb2};

275 141:op_reg_data= {RW_CTRL, 24'h518d42};

276 142:op_reg_data= {RW_CTRL, 24'h518e3d};

277 143:op_reg_data= {RW_CTRL, 24'h518f56};

278 144:op_reg_data= {RW_CTRL, 24'h519046};

279 145:op_reg_data= {RW_CTRL, 24'h5191f8};// AWB top limit

280 146:op_reg_data= {RW_CTRL, 24'h519204};// AWB bottom limit

281 147:op_reg_data= {RW_CTRL, 24'h519370};// red limit

282 148:op_reg_data= {RW_CTRL, 24'h5194f0};// green limit

283 149:op_reg_data= {RW_CTRL, 24'h5195f0};// blue limit

284 150:op_reg_data= {RW_CTRL, 24'h519603};// AWB control

285 151:op_reg_data= {RW_CTRL, 24'h519701};// local limit

286 152:op_reg_data= {RW_CTRL, 24'h519804};

287 153:op_reg_data= {RW_CTRL, 24'h519912};

288 154:op_reg_data= {RW_CTRL, 24'h519a04};

289 155:op_reg_data= {RW_CTRL, 24'h519b00};

290 156:op_reg_data= {RW_CTRL, 24'h519c06};

291 157:op_reg_data= {RW_CTRL, 24'h519d82};

292 158:op_reg_data= {RW_CTRL, 24'h519e38};// AWB control // Gamma 伽玛曲线

293 159:op_reg_data= {RW_CTRL, 24'h548001};// Gamma bias plus on, bit[0]

294 160:op_reg_data= {RW_CTRL, 24'h548108};

295 161:op_reg_data= {RW_CTRL, 24'h548214};

296 162:op_reg_data= {RW_CTRL, 24'h548328};

297 163:op_reg_data= {RW_CTRL, 24'h548451};

298 164:op_reg_data= {RW_CTRL, 24'h548565};

299 165:op_reg_data= {RW_CTRL, 24'h548671};

300 166:op_reg_data= {RW_CTRL, 24'h54877d};

301 167:op_reg_data= {RW_CTRL, 24'h548887};

302 168:op_reg_data= {RW_CTRL, 24'h548991};

303 169:op_reg_data= {RW_CTRL, 24'h548a9a};

304 170:op_reg_data= {RW_CTRL, 24'h548baa};

305 171:op_reg_data= {RW_CTRL, 24'h548cb8};

306 172:op_reg_data= {RW_CTRL, 24'h548dcd};

307 173:op_reg_data= {RW_CTRL, 24'h548edd};

308 174:op_reg_data= {RW_CTRL, 24'h548fea};

309 175:op_reg_data= {RW_CTRL, 24'h54901d};// color matrix 色彩矩阵

310 176:op_reg_data= {RW_CTRL, 24'h53811e};// CMX1 for Y

311 177:op_reg_data= {RW_CTRL, 24'h53825b};// CMX2 for Y

312 178:op_reg_data= {RW_CTRL, 24'h538308};// CMX3 for Y

313 179:op_reg_data= {RW_CTRL, 24'h53840a};// CMX4 for U

314 180:op_reg_data= {RW_CTRL, 24'h53857e};// CMX5 for U

315 181:op_reg_data= {RW_CTRL, 24'h538688};// CMX6 for U

316 182:op_reg_data= {RW_CTRL, 24'h53877c};// CMX7 for V

317 183:op_reg_data= {RW_CTRL, 24'h53886c};// CMX8 for V

318 184:op_reg_data= {RW_CTRL, 24'h538910};// CMX9 for V

319 185:op_reg_data= {RW_CTRL, 24'h538a01};// sign[9]

320 186:op_reg_data= {RW_CTRL, 24'h538b98}; // sign[8:1] // UV adjust UV色彩饱和度调整

321 187:op_reg_data= {RW_CTRL, 24'h558006};// saturation on, bit[1]

322 188:op_reg_data= {RW_CTRL, 24'h558340};

323 189:op_reg_data= {RW_CTRL, 24'h558410};

324 190:op_reg_data= {RW_CTRL, 24'h558910};

325 191:op_reg_data= {RW_CTRL, 24'h558a00};

326 192:op_reg_data= {RW_CTRL, 24'h558bf8};

327 193:op_reg_data= {RW_CTRL, 24'h501d40};// enable manual offset of contrast// CIP 锐化和降噪

328 194:op_reg_data= {RW_CTRL, 24'h530008};// CIP sharpen MT threshold 1

329 195:op_reg_data= {RW_CTRL, 24'h530130};// CIP sharpen MT threshold 2

330 196:op_reg_data= {RW_CTRL, 24'h530210};// CIP sharpen MT offset 1

331 197:op_reg_data= {RW_CTRL, 24'h530300};// CIP sharpen MT offset 2

332 198:op_reg_data= {RW_CTRL, 24'h530408};// CIP DNS threshold 1

333 199:op_reg_data= {RW_CTRL, 24'h530530};// CIP DNS threshold 2

334 200:op_reg_data= {RW_CTRL, 24'h530608};// CIP DNS offset 1

335 201:op_reg_data= {RW_CTRL, 24'h530716};// CIP DNS offset 2

336 202:op_reg_data= {RW_CTRL, 24'h530908};// CIP sharpen TH threshold 1

337 203:op_reg_data= {RW_CTRL, 24'h530a30};// CIP sharpen TH threshold 2

338 204:op_reg_data= {RW_CTRL, 24'h530b04};// CIP sharpen TH offset 1

339 205:op_reg_data= {RW_CTRL, 24'h530c06};// CIP sharpen TH offset 2

340 206:op_reg_data= {RW_CTRL, 24'h502500};

341 207:op_reg_data= {RW_CTRL, 24'h300802}; // wake up from standby, bit[6]

342

343 //set OV5640 to video mode 720p

344 208:op_reg_data= {RW_CTRL, 24'h303521};// PLL input clock =24Mhz, PCLK =84Mhz

345 209:op_reg_data= {RW_CTRL, 24'h303669};// PLL

346 210:op_reg_data= {RW_CTRL, 24'h3c0707}; // lightmeter 1 threshold[7:0]

347 211:op_reg_data= {RW_CTRL, 24'h382047}; // flip

348 212:op_reg_data= {RW_CTRL, 24'h382100}; // mirror

349 213:op_reg_data= {RW_CTRL, 24'h381431}; // timing X inc

350 214:op_reg_data= {RW_CTRL, 24'h381531}; // timing Y inc

351 215:op_reg_data= {RW_CTRL, 24'h380000}; // HS

352 216:op_reg_data= {RW_CTRL, 24'h380100}; // HS

353 217:op_reg_data= {RW_CTRL, 24'h380200}; // VS

354 218:op_reg_data= {RW_CTRL, 24'h3803fa}; // VS

355 219:op_reg_data= {RW_CTRL, 24'h38040a}; // HW (HE)

356 220:op_reg_data= {RW_CTRL, 24'h38053f}; // HW (HE)

357 221:op_reg_data= {RW_CTRL, 24'h380606}; // VH (VE)

358 222:op_reg_data= {RW_CTRL, 24'h3807a9}; // VH (VE)

359 223:op_reg_data= {RW_CTRL, 24'h380805}; // DVPHO (1280)

360 224:op_reg_data= {RW_CTRL, 24'h380900}; // DVPHO (1280)

361 225:op_reg_data= {RW_CTRL, 24'h380a02}; // DVPVO (720)->

362 226:op_reg_data= {RW_CTRL, 24'h380bd0}; // DVPVO (720)->

363 227:op_reg_data= {RW_CTRL, 24'h380c07}; // HTS

364 228:op_reg_data= {RW_CTRL, 24'h380d64}; // HTS

365 229:op_reg_data= {RW_CTRL, 24'h380e02}; // VTS

366 230:op_reg_data= {RW_CTRL, 24'h380fe4}; // VTS

367 231:op_reg_data= {RW_CTRL, 24'h381304}; // timing V offset

368 232:op_reg_data= {RW_CTRL, 24'h361800};

369 233:op_reg_data= {RW_CTRL, 24'h361229};

370 234:op_reg_data= {RW_CTRL, 24'h370952};

371 235:op_reg_data= {RW_CTRL, 24'h370c03};

372 236:op_reg_data= {RW_CTRL, 24'h3a0202}; // 60Hz max exposure

373 237:op_reg_data= {RW_CTRL, 24'h3a03e0}; // 60Hz max exposure

374 238:op_reg_data= {RW_CTRL, 24'h3a0800}; // B50 step

375 239:op_reg_data= {RW_CTRL, 24'h3a096f}; // B50 step

376 240:op_reg_data= {RW_CTRL, 24'h3a0a00}; // B60 step

377 241:op_reg_data= {RW_CTRL, 24'h3a0b5c}; // B60 step

378 242:op_reg_data= {RW_CTRL, 24'h3a0e06}; // 50Hz max band

379 243:op_reg_data= {RW_CTRL, 24'h3a0d08}; // 60Hz max band

380 244:op_reg_data= {RW_CTRL, 24'h3a1402}; // 50Hz max exposure

381 245:op_reg_data= {RW_CTRL, 24'h3a15e0}; // 50Hz max exposure

382 246:op_reg_data= {RW_CTRL, 24'h400402}; // BLC line number

383 247:op_reg_data= {RW_CTRL, 24'h30021c}; // reset JFIFO, SFIFO, JPG

384 248:op_reg_data= {RW_CTRL, 24'h3006c3}; // disable clock of JPEG2x, JPEG

385 249:op_reg_data= {RW_CTRL, 24'h471303}; // JPEG mode 3

386 250:op_reg_data= {RW_CTRL, 24'h440704}; // Quantization sacle

387 251:op_reg_data= {RW_CTRL, 24'h460b37};

388 252:op_reg_data= {RW_CTRL, 24'h460c20};

389 253:op_reg_data= {RW_CTRL, 24'h483716}; // MIPI global timing

390 254:op_reg_data= {RW_CTRL, 24'h382404}; // PCLK manual divider

391 255:op_reg_data= {RW_CTRL, 24'h5001a3}; // SDE on, CMX on, AWB on, scale on

392 256:op_reg_data= {RW_CTRL, 24'h350300}; // AEC/AGC on

393 257:op_reg_data= {RW_CTRL, 24'h301602}; //Strobe output enable

394 258:op_reg_data= {RW_CTRL, 24'h3b070a}; //FREX strobe mode1

395 //strobe flash and frame exposure

396 259:op_reg_data={RW_CTRL, 24'h3b0083}; //STROBE CTRL: strobe request ON, Strobe mode: LED3

397 260:op_reg_data={RW_CTRL, 24'h3b0000}; //STROBE CTRL: strobe request OFF

398

399 default:op_reg_data={RW_CTRL, 24'h000000};

400 endcase

401 end

402

403

404 endmodule