project Abeona #1

1. The compiler must preserve the meaning of the program being compiled.
2. The compiler must improve the input program in some discenible way.

Source program --> Front End --> IR --> Optimization --> Back End --> Target Program

Front End:

1. focuses on understanding the source-language program.
2. translate source program to IR.
3. Scanner-->Parser-->Elaboration
4. Scanner takes a stream of characters and converts it to a stream of classified words:
   "a <- a x 2;" --> (var, "a"), (assign_op, "<-"), (var, "a"), (mult_op, "x"), (const, "2"), (endmark, ";")
5. Parsing is the process of automatically finding derivations:
   1. derivation rules:
      1. assignment sentence -> lhs assign_op rhs
      2. rhs -> var
      3. assign_op -> assign_op
      4. lhs -> var
      5. lhs -> var rest
      6. rest -> op var
      7. rest -> op rest
      8. op -> mult_op, add_op, sub_op, div_op ...
   2. derivate step:
      1. rhs assign_op rhs
      2. var assign_op rhs
      3. var assign_op var rest
      4. var assign_op var op var
      5. var assign_op var mult_op var

Optimization:

1. analysis determines where the compiler can safely and profitably apply the technique.
2. rewrite code into more efficient form.

Back End:

1. foucuses on mapping IR to the target machine instruction set.
2. in this phase we assume IR contains no syntactic or semantic errors.
3. Inst Selection-->Inst Scheduling-->Reg Allocation(all based on IR)
4. ILOC for a <- a x 2:
   loadAI Rarp, @a => Ra // load 'a'
   loadI 2 => R2 // const 2 into 2
   mult Ra, R2 => Ra // Ra <- a x 2
   storeAI Ra => Rarp, @a // write Ra back to 'a'
5. Inst Selection:
   mult Ra, R2 => Ra --> add Ra, Ra => Ra
6. Inst Scheduling, try to find minimize the number of cycles for procedures

IR (TBD: use module in systemverilog as an example):

1. include self-instance
2. include child instance instantiate in this module (use this to build our instance tree)
3. include xmr list
4. include other features (initial/always block, node, assertion...)