【ADSP-BF561 EZ-KIT Lite】DMA

The ADSP-BF561 DMA controllers support both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

 

The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly.

 

Examples of DMA types supported by the ADSP-BF561 DMA Controllers include:

 

l  A single, linear buffer that stops upon completion

l  A circle, auto-refreshing buffer that interrupts on each full or fractionally full buffer

l  1-D or 2-D DMA using a linked list of descriptors

l  2-D DMA using an array of descriptors, specifying only the base DMA address within a common page

 

In addition to the dedicated peripheral DMA channels, each DMA controller has four memory DMA channels provided for transfers between the various memories of the ADSP-BF561 system. These enable transfers of blocks of data between any of the memories – including external SDRAM, ROM, SRAM, and flash memory – with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based auto buffer mechanism.

 

Further, the ADSP-BF561 has a four channel Internal Memory DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories.