NET2272.h 代码分析

 

参考 NET2272 USB 2.0 Peripheral Controller For Revision 1A 文档

 

 #ifndef _ADI_USB_NET2272_H_ #define _ADI_USB_NET2272_H_ #include <drivers/usb/usb_core/adi_usb_objects.h> #if defined(__ADSPBF533__) #include <cdefbf533.h> #elif defined(__ADSPBF537__) #include <cdefbf537.h> #elif defined(__ADSPBF561__) #include <cdefbf561.h> #endif /* NET2272连接到处理其实做了一些假定 比如，我们假设数据长度为16位，所有地址低5位都被使用。 可以通过命令来修改基地址，但是背离USB-LAN EZ-EXTNEDER板设计的修改可能需要改变和重建. */ /* Some assumptions are made as to how the NET2272 is connected to the processor. For example, we assume 16-bit wide data and that all 5 address bits are used. Commands are provided so that you may change the base address, but other deviations from the USB-LAN EZ-EXTENDER design may require changes and a rebuild. */ /* NET2272 寄存器在异步内存块中的基地址 */ /* base address for the NET2272 registers in the async bank */ #ifdef __ADSPBF533__ #define USB_BASE_ADDR 0x20300000 #elif defined(__ADSPBF537__) #define USB_BASE_ADDR 0x20300000 #elif defined(__ADSPBF561__) /*在ADSPBF561中，USB数据传输基地址是 ASYNCMEMORY BANK3, 起始地址为0x2C000000, 终止地址为0x30000000 */ #define USB_BASE_ADDR 0x2C000000 #else #error *** Processor not supported *** #endif extern ADI_DEV_PDD_ENTRY_POINT ADI_USB_NET2272_Entrypoint; /* entry point to the device driver */ /* 主控制寄存器组 */ /** * * Main control register group * NET2272 USB Peripheral controller - Revision 1.2 (Oct 15 2003) * Ref: pg-53 * **/ #define REGADDRPTR 0x00 /* Register address pointer */ #define REGDATA 0x01 /* Register Data */ #define IRQSTAT0 0x02 /* Interrupt status register (low byte) */ #define IRQSTAT1 0x03 /* Interrupt status register (high byte) */ #define PAGESEL 0x04 /* Endpoint page select register */ #define DMAREQ 0x1C /* DMA Request control */ #define SCRATCH 0x1D /* General purpose scratch-pad */ #define IRQENB0 0x20 /* Interrupt Enable Register (low byte) */ #define IRQENB1 0x21 /* Interrupt Enable Register (high byte)*/ #define LOCCTL 0x22 /* Local bus control */ #define CHIPREV_LEGACY 0x23 /* Legacy chip silicon revision */ #define LOCCTL1 0x24 /* Local bus control */ #define CHIPREV_2272 0x25 /* Net2272 Chip Silicon Revision */ /*只有寄存器0x00-0x1F (5 bits)可以通过绝对地址直接访问, 而对于寄存器 0x20-0x40 只能用间接寻址访问*/ /*寄存器0x20-0x40的访问方法：将要访问的寄存器地址放入寄存器REGADDRPTR中，然后通过REGDATA进行寄存器值的读写 */ /* 每个寄存器大小为16bits，所以在计算绝对地址（absolute address）时要讲寄存器地址左移两位，再加上基地址 */ /* * Absloute address only for the registers that are directly accessable * registers 0x00-0x1F for registers 0x20-0x40 accessed indirectly by * placing the to be accessed register in REGADDRPTR and read/write * it from REGDATA */ #define REGADDRPTR_ADDR (USB_BASE_ADDR + (REGADDRPTR << 2)) /* Absloute address of the REGADDRPTR register */ #define REGDATA_ADDR (USB_BASE_ADDR + (REGDATA << 2)) /* Absloute address of the REGDATA register */ #define IRQSTAT0_ADDR (USB_BASE_ADDR + (IRQSTAT0 << 2)) /* Absloute address of the IRQSTAT0 register */ #define IRQSTAT1_ADDR (USB_BASE_ADDR + (IRQSTAT1 << 2)) /* Absloute address of the IRQSTAT1 register */ #define PAGESEL_ADDR (USB_BASE_ADDR + (PAGESEL << 2)) /* Absloute address of the IRQSTAT1 register */ #define DMAREQ_ADDR (USB_BASE_ADDR + (DMAREQ << 2)) /* Absloute address of the DMAREQ register */ #define SCRATCH_ADDR (USB_BASE_ADDR + (SCRATCH << 2)) /* Absloute address of the SCRATCH register */ /* USB 控制寄存器组 */ /** * * USB Control register group * NET2272 USB Periperipheral controller - Revision 1.2 (Oct 15 2003) * Ref: pg-54 * **/ #define USBCTL0 0x18 /* USB control register (low byte) */ #define USBCTL1 0x19 /* USB control register (high byte) */ #define USBFRAME0 0x1A /* USB frame number (low byte) */ #define USBFRAME1 0x1B /* USB frame number (high byte) */ #define OURADDRESS 0x30 /* Our USB address */ #define USBDIAG 0x31 /* USB diagnostic register */ #define USBTEST 0x32 /* USB 2.0 test control register */ #define XCVRDIAG 0x33 /* USB Transceiver diagnostic register */ #define VIRTOUT0 0x34 /* VirtualOut interrupt 0 */ #define VIRTOUT1 0x35 /* VirtualOut interrupt 1 */ #define VIRTIN0 0x36 /* VirtualIN interrupt 0 */ #define VIRTIN1 0x37 /* VirtualIN interrupt 1 */ #define SETUP0 0x40 /* Setup byte 0 */ #define SETUP1 0x41 /* Setup byte 1 */ #define SETUP2 0x42 /* Setup byte 2 */ #define SETUP3 0x43 /* Setup byte 3 */ #define SETUP4 0x44 /* Setup byte 4 */ #define SETUP5 0x45 /* Setup byte 5 */ #define SETUP6 0x46 /* Setup byte 6 */ #define SETUP7 0x47 /* Setup byte 7 */ /* * Absloute address only for the registers that are directly accessable * registers 0x00-0x1F for registers 0x20-0x40 accessed indirectly by * placing the to be accessed register in REGADDRPTR and read/write * it from REGDATA */ #define USBCTL0_ADDR (USB_BASE_ADDR + (USBCTL0 << 2)) /* Absloute address of the USBCTL0 register */ #define USBCTL1_ADDR (USB_BASE_ADDR + (USBCTL1 << 2)) /* Absloute address of the USBCTL0 register */ #define USBFRAME0_ADDR (USB_BASE_ADDR + (USBFRAME0 << 2)) /* Absloute address of the USBFRAME0 register */ #define USBFRAME1_ADDR (USB_BASE_ADDR + (USBFRAME1 << 2)) /* Absloute address of the USBFRAME0 register */ /* Endpoint 寄存器组 */ /** * * Endpoint register group * NET2272 USB Periperipheral controller - Revision 1.2 (Oct 15 2003) * Ref: pg-54 * * Note: These set of EP register are for each endpoint. PAGESEL register * is used to select the endpoint. **/ #define EP_DATA 0x05 /* Endpoint DATA register */ #define EP_STAT0 0x06 /* Endpoint Status register (low byte) */ #define EP_STAT1 0x07 /* Endpoint Status register (high byte) */ #define EP_TRANSFER0 0x08 /* IN endpoint byte count byte0 */ #define EP_TRANSFER1 0x09 /* IN endpoint byte count byte1 */ #define EP_TRANSFER2 0x0A /* IN endpoint byte count byte2 */ #define EP_IRQENB 0x0B /* Endpoint interrupt enable */ #define EP_AVAIL0 0x0C /* Bufferspace/byte count (byte 0) */ #define EP_AVAIL1 0x0D /* Bufferspace/byte count (byte 1) */ #define EP_RSPCLR 0x0E /* Ep response control clear */ #define EP_RSPSET 0x0F /* Ep response set */ #define EP_MAXPKT0 0x28 /* Ep Maximum packet low byte */ #define EP_MAXPKT1 0x29 /* Ep Maximum packet high byte */ #define EP_CFG 0x2A /* Ep configuration */ #define EP_HBW 0x2B /* Ep high bandwidth */ #define EP_BUFF_STATES 0x2C /* Ep buffer states */ /* * Absloute address only for the registers that are directly accessable * registers 0x00-0x1F for registers 0x20-0x40 accessed indirectly by * placing the to be accessed register in REGADDRPTR and read/write * it from REGDATA */ #define EP_DATA_ADDR (USB_BASE_ADDR + (EP_DATA << 2)) /* Absloute address of the EP_DATA register */ #define EP_STAT0_ADDR (USB_BASE_ADDR + (EP_STAT0 << 2)) /* Absloute address of the EP_STAT0 register */ #define EP_STAT1_ADDR (USB_BASE_ADDR + (EP_STAT1 << 2)) /* Absloute address of the EP_STAT1 register */ #define EP_TRANSFER0_ADDR (USB_BASE_ADDR + (EP_TRANSFER0<< 2)) /* Absloute address of the EP_TRANSFER0 register */ #define EP_TRANSFER1_ADDR (USB_BASE_ADDR + (EP_TRANSFER1<< 2)) /* Absloute address of the EP_TRANSFER1 register */ #define EP_TRANSFER2_ADDR (USB_BASE_ADDR + (EP_TRANSFER2<< 2)) /* Absloute address of the EP_TRANSFER2 register */ #define EP_IRQENB_ADDR (USB_BASE_ADDR + (EP_IRQENB << 2)) /* Absloute address of the EP_IRQENB register */ #define EP_AVAIL0_ADDR (USB_BASE_ADDR + (EP_AVAIL0 << 2)) /* Absloute address of the EP_AVAIL0 register */ #define EP_AVAIL1_ADDR (USB_BASE_ADDR + (EP_AVAIL1 << 2)) /* Absloute address of the EP_AVAIL0 register */ #define EP_RSPCLR_ADDR (USB_BASE_ADDR + (EP_RSPCLR << 2)) /* Absloute address of the EP_AVAIL0 register */ #define EP_RSPSET_ADDR (USB_BASE_ADDR + (EP_RSPSET << 2)) /* Absloute address of the EP_AVAIL0 register */ /* 中断状态0/中断使能0 */ /* IRQSTAT0/IRQENB0 interrupt bits pg:56 */ /* NET2272 USB Periperipheral controller - Revision 1.2 (Oct 15 2003) */ /* This bit conveys the interrupt status for Endpoint 0. When set, Endpoint 0's interrupt * status register should be read to determine the cause of the interrupt. This bit is * set independently of the interrupt enable bit. */ #define EP_0_INTERRUPT (1 << 0) /* This bit conveys the interrupt status for Endpoint A. When set, Endpoint A's interrupt * status register should be read to determine the cause of the interrupt. This bit is * set independently of the interrupt enable bit. */ #define EP_A_INTERRUPT (1 << 1) /* This bit conveys the interrupt status for Endpoint B. When set, Endpoint B's interrupt * status register should be read to determine the cause of the interrupt. This bit is * set independently of the interrupt enable bit. */ #define EP_B_INTERRUPT (1 << 2) /* This bit conveys the interrupt status for Endpoint C. When set, Endpoint C's interrupt * status register should be read to determine the cause of the interrupt. This bit is * set independently of the interrupt enable bit. */ #define EP_C_INTERRUPT (1 << 3) /* This bit is set when of the Virtual Endpoints interrupts is set */ #define VIRTUAL_EP_INTERRUPT (1 << 4) /* This bit is set when one of the Virtual Endpoint interrupts is set */ #define SETUP_PKT_INT (1 << 5) /* For IN endpoints, this bit indicates that EOT# has been asserted, the EP_TRANSFER counter * reaches zero during a DMA, or the corresponding EP_TRANSFER counter is loaded with a 0. * For OUT endpoints, this bit indicates that EOT# has been asserted, or that a short packet * has been received and the endpoint buffers have gone empty. Writing a 1 clears this status bit. * This bit is set independently of the corresponding interrupt enable bit */ #define DMA_DONE_INT (1 << 6) /* This bit indicates when a start-of-frame packet has been received by the NET2272 */ #define SOF_INT (1 << 7) #define IRQSTAT0_ALL_INT ((SOF_INT) | (DMA_DONE_INT) | (SETUP_PKT_INT)) /* 中断状态1/中断使能1 */ /* IRQSTAT1/IRQENB1 interrupt bits pg:57/59 */ /* NET2272 USB Periperipheral controller - Revision 1.2 (Oct 15 2003) */ /* Bit 7 is Reset Status which can not be written. When set, this bit indicates that either the RESET# pin is * asserted, or a USB root port reset is currently active. */ /* This bit indicates a change in state of the root port reset detector. Writing a 1 clears this status bit. */ #define ROOT_PORT_RESET_INT (1 << 6) /* When set, this bit indicates that a device resume has occured. Writing a 1 clears this status bit. */ #define RESUME_INT (1 << 5) /* This bit is set whenever there is a change in the Suspend Request Interrupt state (bit 3 of this register). * Writing a 1 clears this status bit */ #define SUSPEND_RQT_CHANGE_INT (1 << 4) /* This bit is set when the NET2272 detects a USB Suspend request from the host. The Suspend Request state cannot be * set or cleared by writing this bit. Instead, writing a 1 to this bit puts the NET2272 into the low-power suspend mode */ #define SUSPEND_RQT_INT (1 << 3) /* VBUS Interrupt. When set, this bit indicates that a change occured on the VBUS input pin. Read the USBCTL1 register * for the current state of this pin. Writing a 1 clears the status bit. */ #define VBS_INT (1 << 2) /* This bit is set when an IN or OUT token indicating Control Status has been received. Writing a 1 clears this status bit. */ #define CONTROL_STATUS_INT (1 << 1) #define IRQSTAT1_ALL_INT ((ROOT_PORT_RESET_INT) | (RESUME_INT)| (SUSPEND_RQT_CHANGE_INT) | (SUSPEND_RQT_INT) |/ (VBS_INT) | (CONTROL_STATUS_INT)) /* Endpoints pg:57 */ /* Page Select. The NET2272 uses a paged architecture for accessing the registers associated with each endpoint. This field * selects which set of endpoint registers can be accessed */ #define EP0 0x00 #define EPA 0x01 #define EPB 0x02 #define EPC 0x03 /* Endpoint 状态位0 */ /* EPSTAT0 pg:68 */ /* This bit is set when the endpoint packet buffer is full. For an IN endpoint, the currently selected * buffer has a count of MaxPkt bytes, or no buffer is available to the local local side for writing * (no space to write). For an OUT endpoint, there is a buffer available on the local side, and there are * MaxPkt bytes available to read (no space to write). For an OUT endpoint, there is a buffer avaiable on * the local side, and there are MaxPkt bytes avaiable to read (entire packet is avaiable for reading). */ #define EP_BUFFER_FULL (1 << 7) /* For an IN endpoint, a buffer is avaiable to the local side for writing up to MaxPkt bytes. This bit is * set when the endpoint buffer is empty. For an OUT endpoint, the currently selected buffer has a count * of 0, or no buffer is available on the local side (nothing to read). */ #define EP_BUFFER_EMPTY (1 << 6) /* This bit is set when a short data packet is received from the host by this endpoint, and the NAK OUT Packets Mode * bit of EP_RSPSET register is set. Writing a 1 clears this status bit. If this bit is set and another OUT token is * received, a NAK is returned to the host if another OUT packet is sent to this endpoint. This bit can also be * controlled by the EP_RSPCLR and EP_RSPSET registers. */ #define EP_NAC_OUT_INT (1 << 5) /* This bit is set when the length of the last packet was less than the Maximum Packet Size (EP_MAXPKT). * Writing a 1 clears this bit */ #define EP_SHORT_PKT_TFRD_INT (1 << 4) /* This bit is set when a data packet is received from the host by this endpoint. Writing 1 clears this bit */ #define EP_DATA_RCVD_INT (1 << 3) /* This bit is set when a data packet is transmitted from the endpoint to the host. Writing 1 clears this bit */ #define EP_DATA_XMTD_INT (1 << 2) /* This bit is set when a Data OUT token has been received from the host. This bit is also set by PING tokens (in high-speed only). * Writing a 1 clears this bit */ #define EP_DATA_OUT_TOKEN_INT (1 << 1) /* This bit is set when a Data IN token has been received from the host. Writing a 1 clears this bit */ #define EP_DATA_IN_TOKEN_INT (1 << 0) #define EP_STAT0_INT_ALL ( (EP_NAC_OUT_INT) | (EP_SHORT_PKT_TFRD_INT) | (EP_DATA_RCVD_INT) | (EP_DATA_XMTD_INT) | / (EP_DATA_OUT_TOKEN_INT) | (EP_DATA_IN_TOKEN_INT) ) /* Endpoint 状态位1 */ /* EPSTAT1 pg:69 */ /* Writing a 1 to this bit causes the packet buffer to be flushed and the coressponding EP_AVAIL register to be cleard. * This bit is self-clearing. This bit should always be written after an endpoint configuration (direction, address, etc.) * has been changed. This bit should not be asserted during a split-mode DMA if Page Select is selecting another endpoint. */ #define EP_BUFFER_FLUSH (1 << 7) /* bit 6 : Local OUT ZLP. When set, this bit indicates that the current local buffer contains a * zero length packet */ /* The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged * with a STALL. Writing a 1 clears this bit. */ #define EP_USB_STALL_SENT (1 << 5) /* The last USB IN packet could not be provided, and was acknowledged with a NAK. Writing a 1 clears this bit. */ #define EP_USB_IN_NACK_SENT (1 << 4) /* The last USB IN data packet transferred was successfully acknowledged with an ACK from the host. Writing a 1 * clears this bit. */ #define EP_USB_IN_NACK_RCV (1 << 3) /* The last USB OUT data packet could not be accepted, and was acknowledged with an ACK to the host. Writing a 1 * clears this bit */ #define EP_USB_OUT_NACK_SENT (1 << 2) /* The last USB OUT data packet transferred was successfully ackonwedged with an ACK to the host. Writing a 1 clears * this bit */ #define EP_USB_OUT_ACK_SENT (1 << 1) /* For an IN endpoint, the last USB packet transmitted was not acknowedged by the Host PC, indicating a bus error. * The Host PC will expect the same packet to the retransmitted in response to the next IN token. For an OUT endpoint, * the last USB packet received had a CRC or bit-stuffing error, and was not ackonwedged by the NET2272. The Host PC will * retransmit the packet. Writing a 1 clears this bit */ #define EP_USB_TIMEOUT (1 << 0) #define EP_STAT1_INT_ALL ( (EP_BUFFER_FLUSH) | (EP_USB_STALL_SENT) | (EP_USB_IN_NACK_SENT) | (EP_USB_IN_NACK_RCV) | / (EP_USB_OUT_NACK_SENT) | (EP_USB_OUT_ACK_SENT) | (EP_USB_TIMEOUT)) /* Endpoint Respond Clear and Endpoint Respond Set register */ /* EP_RSPCLR/EP_RSPSET regisrs pg:71&72*/ /* This bit is set when a short data packet is received from the host by this endpoint, and the NAK OUT Packets Mode bit * is set and another OUT token is received, a NAK is returned to the host if another OUT packet is sent to this endpoint. * This bit can also be cleared by a bit in the EP_STAT0 register */ #define EP_ALT_NAK_OUT_PACKETS (1 << 7) /* When set, the DATA Packet Received and Data Packet Transmitted interrupts for status phase packets are not set */ #define EP_HIDE_STATUS_PHASE (1 << 6) /* When set, this bit allows automatic validation of maximum length packets. Automatic validation meas that if there are * EP_MAXPKT bytes in the endpoint buffer, the data is returned to the USB host in response to the next IN token without * being manually validated by the local CPU. This is the normal mode of operation for endpoint transactions and is the * default state for this bit. When this bit is clear, packets must be manually validated. Writing zero to EP_TRANSFER0 when * EP_TRANFER1 and EP_TRANSFER2 have a value of 0 validates the contents of this IN endpoint buffer regardless of the state of * the Auto Validate bit; if the buffer is empty, writing zero to EP_TRANSFER0 validates a Zero Length Packet. */ #define EP_AUTO_VALIDATE (1 << 5) /* This bit is only used for INTERRUPT endpoints. For normal interrupt data, this bit should be set to zero and standard data * toggle protocol is followed. When this interrupt endpoint is used for isochronous rate feedback information, this bit should * be set high. In this mode the data toggle bit is changed after each packet is sent to the host without regard to handshaking */ #define EP_INTERRUPT_MODE (1 << 4) /* This bit is only used for endpoint 0. This bit is automatically set when a setup packet is detected. While the bit is set, a control * status phase will be ackonwledged with a NAK. Once cleared, the proper response will be returned to the host (ACK for Control Reads and * zero-length packets for Control Writes). */ #define EP_CONTROL_STATUS_PHASE_HS (1 << 3) /* This bit is only used for OUT endpoints. When NAK OUT Packets Mode is true, the NAK OUT Packets bit is set whenever a short packet is * received by this endpoint */ #define EP_NAK_OUT_PACKETS_MODE (1 << 2) /* This bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit. Under * normal operation, the toggle bit is controlled automatically, so the local CPU does not need to use this bit */ #define EP_TOGGLE (1 << 1) /* This bit is used to clear the endpoint stall bit. When an Endpoint Set Feature Standard Request to the halt bit is detected by the local CPU, * it must write a 1 to this bit. Reading this bit returns the current state of the endpoint halt bit. For endpoint 0, the halt bit is automatically * cleared when another Setup packet is received.*/ #define EP_HALT (1 << 0) /* USB Control Register bits */ /* USBCTL0 register bit */ /* When clear, the wake-up condition is not detected. When set, the root port wake-up condition is detected when activity * is detected on the USB */ #define ROOT_PORT_WAKEUP_ENABLE (1 << 5) /* When clear, the NET2272 does not appear to be connected to the USB host. When set, the NET2272 appears to be connected to * USB host. This bit should not be set until the configuration registers have been programmed. When operating as a bus-powered device, * the registers should be programmed and this bit should be set promptly after VBUS has been detected. */ #define USB_DETECT_ENABLE (1 << 3) /* When clear, asserting CS# will not cause a device remote wakeup. When set, this bit enables the assertion of CS# to initiate a device * remote wakeup. */ #define IO_WAKEUP_ENABLE (1 << 1) #define USBCTL0_ENABLE_ALL ((ROOT_PORT_WAKEUP_ENABLE) | (USB_DETECT_ENABLE) | (IO_WAKEUP_ENABLE) ) /* NET2272中位于地址 0x00 - 0x1F 的寄存器可以地址直接访问 */ /* 剩下的位于 0x20 - 0x40 的寄存利用REGADDRPTR 和 REGDATA 间接访问 */ /* * Use direct addressing for NET2272 registers sitting at 0x00 - 0x1F. The rest * (0x20 - 0x40) have to use indirect addressing with REGADDRPTR. * */ /* OUT BYTE DIRECT */ inline void _outpb_d(unsigned int addr,unsigned char value) { unsigned char volatile *paddr = (unsigned char volatile*)(addr); csync(); *paddr = value; csync(); } /* OUT WORD DIRECT */ inline void _outpw_d(unsigned int addr,unsigned short value) { unsigned short volatile *paddr = (unsigned short volatile*)(addr); csync(); *paddr = value; csync(); } /* OUT BYTE INDIRECT */ inline void _outpb_ind(int reg_addr,unsigned char value) { unsigned char volatile *paddr = (unsigned char volatile*)REGADDRPTR_ADDR; /* put the register address in the REGADDRPTR register */ csync(); *paddr = reg_addr; csync(); paddr = (unsigned char volatile*)(REGDATA_ADDR); *paddr = value & 0xff; csync(); } /* OUT WORD INDIRECT */ inline void _outpw_ind(int reg_addr,unsigned short value) { unsigned short volatile *paddr = (unsigned short volatile*)REGADDRPTR_ADDR; /* put the register address in the REGADDRPTR register */ csync(); *paddr = reg_addr; csync(); paddr = (unsigned short volatile*)(REGDATA_ADDR); *paddr = value & 0xffff; csync(); } /* IN BYTE DIRECT */ inline char _inpb_d(unsigned int addr) { volatile unsigned char r_val; unsigned char volatile *paddr = (unsigned char volatile*)(addr); csync(); r_val = *paddr; return(r_val&0xff); } /* IN WORD DIRECT */ inline short _inpw_d(unsigned int addr) { volatile unsigned short r_val; unsigned short volatile *paddr = (unsigned short volatile*)(addr); csync(); r_val = *paddr; return(r_val& 0xffff); } /* IN BYTE INDIRECT */ inline char _inpb_ind(int reg_addr) { volatile unsigned char r_val; unsigned char volatile *paddr = (unsigned char volatile*)REGADDRPTR_ADDR; /* put the register address in the REGADDRPTR register */ csync(); *paddr = reg_addr; csync(); paddr = (unsigned char volatile*)REGDATA_ADDR; r_val = *paddr; csync(); return(r_val& 0xff); } /* IN WORD INDIRECT */ inline short _inpw_ind(int reg_addr) { volatile unsigned short r_val; unsigned short volatile *paddr = (unsigned short volatile*)REGADDRPTR_ADDR; /* put the register address in the REGADDRPTR register */ csync(); *paddr = reg_addr; csync(); paddr = (unsigned short volatile*)REGDATA_ADDR; r_val = *paddr; csync(); return(r_val& 0xffff); } #endif /* _ADI_USB_NET2272_H_ */