s5pv210 datasheet_system_clock controler

3 CLOCK CONTROLLER
This chapter describes the clock management unit (CMU) supported by S5PV210. The system controller
(SYSCON) manages CMU and power management unit (PMU) in S5PV210.
3.1 CLOCK DOMAINS
S5PV210 consists of three clock domains, namely, main system (MSYS), display system (DSYS), and peripheral
system (PSYS), as shown in Figure 3-1.
• MSYS domain comprises Cortex A8 processor, DRAM memory controllers (DMC0 and DMC1), 3D, internal
SRAM (IRAM, and IROM), INTC, and configuration interface (SPERI). Cortex A8 supports only synchronous
mode, and therefore it must operate synchronously with 200MHz AXI buses.
• DSYS domain comprises display related modules, including FIMC, FIMD, JPEG, and multimedia IPs (all other
IPs mentioned in X, L, and T blocks), as shown in Figure 3-1.
• PSYS domain is used for security, I/O peripherals, and low power audio play.
• Each bus system operates at 200 MHz (maximum), 166 MHz, and 133 MHz, respectively. There are
asynchronous bus bridges (BRG) between two different domains.