vhdl 编写counter ，模拟钟表

    好久没玩过FPGA了，回想起当时和张胤一起写的SOPC系统还真是怀念啊，自己编写的CPU，自己编写的外设驱动（软件+硬件），自己定义的汇编语言，自己编写的汇编器，基于这些自己的东西写自己的应用程序，那些好玩的游戏~ 怀念，有时间一定写篇文章纪念一下。

     选这个课，是想回忆下基本的VHDL知识，什么东西不用都会忘掉的。这是一个很简单的程序，有时分秒的功能，没有任何管脚指定，仅仅用modelsim仿真了一下。

      counter的代码：

 

---------------------------------------------------------------
--
--      Author: Chaos Lee(ID:sy1106508)
--      Name: A simple counter.
--      Date: 2012/05/06
--
---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
 port(
   clk: in std_logic;
   clr: in std_logic;
   sec: out std_logic_vector(5 downto 0);
   min: out std_logic_vector(5 downto 0);
   hour: out std_logic_vector(4 downto 0)
   );
end entity;
architecture behave of counter is
begin
  process(clk,clr)
 variable sec_cnt: integer range 0 to 59;
 variable min_cnt: integer range 0 to 59;
 variable hour_cnt: integer range 0 to 23;
  begin
  if(clr = '0') then
   sec_cnt := 0;
   min_cnt := 0;
   hour_cnt := 0;
  else
   if(clk'event and clk = '1')then
    if(sec_cnt = 59) then
     sec_cnt := 0;
     if(min_cnt = 59) then
      min_cnt := 0;
      if(hour_cnt = 23) then
       hour_cnt := 0;
      else
       hour_cnt := hour_cnt + 1;
      end if;
     else
      min_cnt := min_cnt + 1;
     end if;
    else
     sec_cnt := sec_cnt+1;
    end if;
   end if;
  end if;
  sec <= conv_std_logic_vector(sec_cnt,6);
  min <= conv_std_logic_vector(min_cnt,6);
  hour <= conv_std_logic_vector(hour_cnt,5);
  end process;
end architecture;

      modelsim的测试代码：

    

------------------------------------------------------------
--
--    Author: Chaos Lee (ID:sy1106508)
--    Name: counter_tb
--    Description: A testbench aiming to verify the counter simulating a clock
--    Date: 2012/05/06
--
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_tb is
end entity;

architecture behave of counter_tb is
component counter is
 port(
   clk: in std_logic;
   clr: in std_logic;
   sec: out std_logic_vector(5 downto 0);
   min: out std_logic_vector(5 downto 0);
   hour: out std_logic_vector(4 downto 0)
   );
end component;

signal clk_tb:std_logic;
signal clr_tb:std_logic;
signal sec_tb:std_logic_vector(5 downto 0);
signal min_tb:std_logic_vector(5 downto 0);
signal hour_tb:std_logic_vector(4 downto 0);

begin
  u1:counter port map (
      clk => clk_tb ,
      clr => clr_tb ,
      sec => sec_tb ,
      min => min_tb ,
      hour => hour_tb
      );
  test_bench:process
  begin
    clr_tb <='0' , '1' after 20ns;
    clk_tb <= '1';
    for i in 10000 downto 0 loop
      wait for 10 ns;
      clk_tb <= not clk_tb;
    end loop;
  wait;
  end process;
end architecture;