verilog的input和output的类型

verilog的input和output是什么类型？
reg and wire specify how the object will be assigned and are therefore only meaningful for outputs.
reg和wire指定如何分配对象，因此仅对输出有意义。

If you plan to assign your output in sequential code,such as within an always block, declare it as a reg (which really is a misnomer for “variable” in Verilog). Otherwise, it should be a wire, which is also the default.
如果计划在顺序代码中分配输出，例如在always块中，则将其声明为reg（这实际上是Verilog中“变量”的误称）。 否则，它应该是wire型的，这也是默认值。

verilog模块写成以下这样简便易读
module mux4( inputa_i, b_i,c_i, d_i,
input [1:0] sel_i,
outputz_o);